The Logic Design Of 10GSPS Arbitrary Waveform Synthesis Module

With advantages such as high frequency resolution,strong frequency stability and user-defined complex waveform output,arbitrary waveform generator has been widely used in electronic measurement field.In order to meet the higher requirements for the frequency bandwidth and waveform complexity,the thesis studied the implementation of 10 GSPS arbitrary waveform synthesis module logic design.The main contributions are as follows:1.The overall scheme design of waveform synthesis module.Based on the project's 10 GSPS sampling rate and 4GByte storage depth requirements,we selected the appropriate DAC and DDR3 SDRAM.To solve the problem of uneven data flow caused by selecting DDR3 SDRAM,the asynchronous FIFO was used in the data processing module to achieve data buffering and data rate adjustment.In the read and write control module,the read and write control of waveform data was realized by controlling the state jump of the state machine.Aiming at the problem that the repeated waveform segments contained in the complex sequence wave will waste storage space,a waveform synthesis instruction set is designed.By storing,reading,and analyzing the instructions,the repeated output of the waveform sequence is completed to save storage space.2.The design and implementation of sub-modules.This part analyzed the functions and parameters of three sub-modules.Then the functions of these sub-modules were implemented by using the Verilog HDL language.3.Testing and verification.A test platform was set up to verify the the waveform reading and writing control function of arbitrary waveform generator.The function of sequence waveform output and the quality of output waveform was verified in this part.The test and verification results show that the designed waveform synthesis module can achieve the functions of reading and writing control of waveform data and output of complex sequence waveform.The waveform quality meets the requirements of the project.