10GSPS Arbitrary Waveform Systhesis Module Hardware Design

Arbitrary waveform generator can produce conventional waveform and user-defined waveform,which is widely used in modern testing field.However,with the requirement of signal source in the field of testing is increasing,which leads to the development of arbitrary waveform generator towards high sampling rate and deep storage.High sampling rate increase the bandwidth of the output signal while also helping to improve signal quality,while deeper storage depth can better describe waveform details and perform more complex waveforms.Therefore,increasing the sampling rate and storage depth has become a hot and difficult problem in the research of arbitrary waveform generator at present.This paper studies the synthesis waveform of high speed and deep storage,JESD204 B interface which transmission speed is faster,data pins are much less,is widely used in high-speed DAC.DDR3 SDRAM has the advantages of large storage capacity and fast access speed,and has become the key research object of high-speed and deep data storage.Based on the above situation,designs the hardware circuit of double channel synchronous output arbitrary waveform synthesis module with maximum storage depth of 4G point,10 GSPS sampling rate and signal bandwidth of 2GHz,the concrete work content is as follows:1.Arbitrary waveform synthesis circuit design.According to the reading and writing characteristics of DDR3 SDRAM,combined with the structural characteristics and advantages and disadvantages of direct digital waveform synthesis(DDWS)and direct digital Frequency synthesis(DDFS),the arbitrary waveform synthesis using DDWS is determined,and the structure of "FPGA+DDR3 SDRAM+DAC" is adopted.Referring to the design index,JESD204 B interface DAC is selected,then the synchronization scheme and clock generation scheme are determined according to the deterministic delay characteristic and clock requirements of the interface,and the hardware circuit design of the system is completed according to the practical application.2.FPGA logic design.The PCIe core is used to realize the communication between the FPGA and the host computer,so that the host computer can send waveform data and waveform synthesis command through the PCIe bus.After the width and clock conversion of the AXI4 interface data of the PCIe DMA,write data to the DDR3 SDRAM memory bar through DDR3 interface control IPAXI Crossbar is used to address the AXI4-MM interface of PCIe DMA,and the channel interface of waveform data storage is sent to the DDR3 interface control IP after clock and data width conversion to realize the DDR3 SDRAM waveform data storage.DDR3 SDRAM data reading operation design is completed based on AXI DMA IP,and the reading rate is greater than 10GB/s in SGDMA mode.At the same time,the corresponding waveform synthesis control command storage,command reading module and descriptor chain generation module are designed to generate the descriptor chain required by SGDMA according to the custom waveform synthesis command.Finally,the design of waveform data sending terminal and DAC synchronous control is completed,and the dual-channel waveform synchronous output is realized.The tests and verification show that the arbitrary waveform synthesis module designed in this paper supports maximum 10 GSPS sampling rate;Dual channel synchronous output arbitrary waveform and up to 2GHz sine wave,and the synchronization deviation is less than 25ps;Maximum 4G point storage depth.