Design And Implementation Of Timing Skew Mismatch Compensation Algorithm Based On Digital Filter Bank In TIADC

The sampling speed and accuracy of Analog to Digital Converter(ADC)is the key to modern digital signal processing systems.The sampling speed and accuracy of traditional ADCs are subjected to the development of device and process technology,which have approached the limits of existing processes.Time-interleaved(TI)architecture can effectively solve this problem.However,the mismatch between different channels of the TIADC greatly reduces the sampling accuracy of the TIADC and must be calibrated.Foreground calibration has high calibration accuracy and low complexity.Although foreground calibration can't follow mismatch parameter drifts,it is suitable for TIADC mismatch calibration when environment is stable such as instrument.In this thesis,the perfect reconstruction algorithm is used to design the Finite Impulse Response(FIR)filter bank to calibrate the time skew mismatch in TIADC.When the perfect reconstruction method solves the coefficients of the filter bank,the calibration effect of the filter bank on the time skew mismatch and the amplitude distortion of the filter bank are mutually restricted.If the amplitude distortion is too large,the filter bank has no practical application value.Aiming at this issue,the amplitude distortion parameter based on the original design parameters is introduced in this thesis to determine the maximum calibration effect of the filter bank as well as maximizes the calibration of the time skew mismatch of the filter bank without affecting the 3dB bandwidth of the filter bank.Optimization algorithms are used to solve the model in this thesis.By analyzing and comparing the accuracy and speed of the genetic algorithm and artificial fish swarm algorithm when solving the model,the genetic algorithm is chosen.The introduction of the amplitude distortion parameter can maintain the calibration accuracy while reducing the complexity of the filter bank.In order to verify the algorithm in this thesis,a 4 channel,14-bit,sampling rate of 320 MSps TIADC system is designed.FPGA is used to calibrate the TIADC system.Limited to the actual sampling data accuracy,the calibration filter bank designed based on this algorithm uses a 15-order filter bank to calibrate the spurious amplitude caused by time skew mismatch in the TIADC to below-77 dBc,while the ENOB of the TIADC system is raised above 3 bits.