Research And Design Of Baseband Chip For 76-81GHz Automotive Radar System

The rapid development of automotive radar has brought a richer driving experience to car driving.Among them,the 76-81GHz millimeter wave band radar has the advantages of longer detection distance,higher detection accuracy,smaller antenna/chip size and stronger power of penetration,and becomes the current research hotspot of millimeter wave automotive radar.Based on the 55-nm CMOS process,this paper is devoted to the research and implementation of high-precision,high-speed successive approximation register analog-to-digital converter（SAR ADC）and high linearity,large dynamic range Active-RC analog baseband circuit in 76-81GHz millimeter-wave automotive radar systems.The main research results include:（Ⅰ）According to the ranging and speed detection of the 76-81GHz millimeter-wave automotive radar system,considering the millimeter-wave propagation path loss and the RF front-end link budget,the design specifications of the analog-to-digital converter and analog baseband circuit in this paper are given.（Ⅱ）Based on the asynchronous dual-loop structure with V_CM-based switching timing,a 12-bit 50MS/s SAR ADC chip is designed.The main modules include:complementary CMOS bootstrap sample-and-hold switch,this structure significantly reduces signal leakage and guarantees the linearity of the switch.The simulation results show that the voltage drop of the switch moment is only 40μV.The addition of an N-type diode in the first stage of the comparator effectively suppresses the interference of the clock feedthrough on the signal,compared with the traditional structure,the effective number of bits（ENOB）of the ADC is improved by at least 2 bits.The improved SAR logic cell not only greatly reduces the data establishment time to more than 100ps,but also saves 50%of the layout area;the DAC array adopts a split placement,which is beneficial to the linearity of the SAR ADC system.The DAC static parameters INL and DNL are-0.47LSB and 0.88LSB respectively.The core area of the chip layout is 760μm×240μm.The post-simulation results show that under the 10MHz input signal,the 27°C TT process,the effective number of bits（ENOB）in the ADC system reaches 10.8bit,the spurious free dynamic range（SFDR）reaches 75.86d Bc,and the current consumption is 0.989 m A,Fo M is 13.3f J/（c.-s）（Ⅲ）A high linearity and large dynamic range analog baseband circuit is designed,which includes AC coupling,pre-amplifier,improved Tow-Thomas Biquad low-pass filter unit,DC offset cancellation circuit and output buffer.The stages of second-order nodes,the choice of approximate function and the corresponding Q value allocation are given.The differential Op Amp in the Biquad adopts feed-forward path technology to achieve a 6-times increase in bandwidth without adding additional power consumption.Four-stage cascaded Tow-Thomas Biquad realizes 6d B/step gain tuning step.The baseband chip layout size is 650μm×230μm.In 27°C TT process,the simulation results show that the gain range is-18-+71d B,the bandwidth is constant at 12.6MHz,OP1d B at high gain reaches 7.44d Bm（1490m Vpp）.When gain is 71d B,the noise figure is 21.49dB.