Research And Implementation Of Cascaded Codes In Data Link System

The data link is an important part of the battlefield communication system,which ensures that the airborne information,ground control information and relay forwarding information can be shared in time,and synchronous operations can be realized quickly.The reliability of information transmission in war is an important indicator that Imust be considered in the data chain,so anti-jamming technology is one of the core technologies of the data link.In order to improve the reliability of the data link system,error control technology must be introduced.Therefore,it is of great significance to study the channel coding technology of the data link system and select the coding method suitable for the data link.This paper mainly studies the channel coding technology of downlink,in a self-defined missile data link system.On the basis of discussing the research trends of channel coding in missile-borne data link at home and abroad and studying the common channel coding schemes in missile-borne data link,the design scheme of downlink channel coding in this data link is analyzed.After many comparisons and considerations,concatenated code(RS code +interleaving + convolutional code)is chosen as downlink channel coding.The related algorithms of concatenated code and its implementation on FPGA are mainly studied.Firstly,the basic principles of concatenated codes are studied.The encoding and decoding principles of RS code,:interleaved code and convolutional code are analyzed respectively.The related algorithms are studied based on the deduction of mathematical formulas and the use of MATLAB platform.Secondly,the hardware description of the concatenated coder and decoder is simulated and realized logically.The hardware implementation methods of RS decoder,Viterbi decoder and convolutional interleaver are introduced in detail.Thirdly,the connection module of each part of the concatenated code is designed.The hardware implementation method of the whole system's Xilinx-based FPGA development board is given,and it is simulated and verified on the Vivado platform.Finally,the error-correcting performance of the concatenated code scheme is analyzed,and the concatenated code is tested on-line by using the logic analyzer ILA.After testing,the concatenated error-correcting code can correct random errors with at least one symbol per interval of 8 symbols(2-bit binary number)and burst errors with a maximum of 140 consecutive bits.It can effectively reduce the error rate of the missile-borne data link system and meet the design requirements of the data link.