Research For Area Cost Of Custom Instruction Based On The FPGA Architecture

With the development of embedded technology,high performance and programmability become the most important design objectives for system on chip.Without changing the whole structure,reconfigurable processor can design specific instruction for special application to improve system performance,shorten design cycles and reduce design costs.According to specific target applications and special physical device,selection process of dedicated instruction is known as custom instruction.Many studies have related to the automation process of custom instruction,but mainly focused on the selection algorithm research.From the perspective of area estimation and area optimization for custom instruction,researches of the article are about the automation of custom instruction as follows:Firstly,use the area cost estimation approach based on basic cell to accurately estimate the area cost of custom instruction.According to the characteristics of island-style FPGA architecture,use the basic cell as the smallest unit of intermediate representation to divide a custom instruction.First,the process enumerates all the possible basic cell instances of custom instruction,then checks the validity of each basic cell and chooses a minimum set of basic cell to overlap the original intermediate representation of custom instruction,finally use the model based on the basic cell to accurately estimate the area of custom instructions.Each valid basic cell only needs a single FPGA logic unit to be realized,therefore indirectly estimate the number of FPGA logic units to use by counting the number of basic cells,when the datapath of custom instruction is realized.Then,on the basis of the basic cell partition,use the approach of instruction merging to optimize area of custom instructions.After partition the custom instruction to a minimum set of basic units,every basic cell from the collection is divided to "log" and "arith" parts,and then merge two basic cell from different custom instructions according to whether use the new multiplexer.The new basic cell after merging can complete the function of the original basec cell by timesharing,but only needs to use a single FPGA logic cell to be realized.Method of instruction merging differs from the method of resource sharing,and maximizes the computing power of look-up table rather than maximizing the sharing of the same nodes,and makes the function of two original basic cells to only need one FPGA logic unit to be realized.