Research On Coding And Decoding Of Rate-compatible Low-density Parity-check Codes

Channel coding is a communication technology that can improve the reliability of information transmission and has been widely used.LDPC code is a linear block code whose performance approaches the Shannon limit.Its error correction capability and implementation complexity make it one of research hotspots in the channel coding field.The rate of LDPC code cannot be arbitrarily changed.This paper combines LDPC code with rate-compatible algorithm to improve the adaptability of LDPC code to different channel environments,and implements a rate-compatible LDPC codec on FPGA.Firstly,this paper introduces the related theory of LDPC codes,including the matrix representation of LDPC codes and their Tanner graphs.On this basis,the concepts of the rings in LDPC codes and the degree distribution of nodes are introduced.Subsequently,three common LDPC code encoding algorithms and various soft-hard-decision decoding algorithms are introduced,and their complexity and advantages and disadvantages are compared and analyzed.Then,it introduces the puncturing algorithm based on the recovery tree in code rate compatible algorithm,including the concept of recovery tree,the grouping/sorting algorithm and the centralized puncturing algorithm.Secondly,the structure characteristics of check matrix and generator matrix of(2048,1024)LDPC code applied to deep space communication under the CCSDS standard are analyzed,and the appropriate degrees of parallelism of encoder and decoder are chosen for implementation.The main parameters of the decoding implementation are determined by the MATLAB simulation results,including the quantization method and the number of iterations.At the same time,an improved scheme is proposed for the centralized puncturing algorithm.By improving the position selection method of the punctured node,the LDPC code punctured by the improved algorithm is better than the LDPC code punctured by the original algorithm at the same code rate.This difference in coding gain is more pronounced on high-rate LDPC codes.Finally,FPGA-based rate-compatible LDPC codec is implemented.The encoder uses a partial parallel coding architecture based on SRAA circuits.The decoder structure is a partial parallel decoding architecture based on a minimum sum algorithm.The hardware implementation adopts the top-down modular design concept,and codec is tested on FPGA and the system is tuned.An LDPC codec with a code rate range of 0.4 to 0.8 is implemented.The codec flexibly adjusts the information transfer rate on the premise of ensuring communication reliability.