Research And Implementation Of BCH Encoder And Decoder For DVB-S2 System

With the rapid development of digital technology,digitalization has been more and more applied to real life.In the field of video broadcasting,satellite digital television has replaced cable television.The transmission and processing of television signals need to be performed according to certain standards.Now the most widely used standard in the world is the DVB-S2.It is the second generation digital video broadcasting standard promulgated by ETSI.Its powerful features and excellent performance have attracted widespread attention.The FEC of the DVB-S2 system uses channel concatenation of BCH and LDPC for channel coding.Channel coding technology is to improve the system's immunity.An error occurs because of the signal interfered by the channel during the satellite channel transmission.Using the channel coding technology can be detected and corrected the error.This article has studied the BCH code of the forward error correction system in the DVB-S2 standard.First,basic theoretical knowledge such as channel coding and error correction code related concepts are introduced.Then,the definition,properties,coding algorithm and decoding algorithm of BCH code are deeply studied.According to the application requirements of BCH code in DVB-S2 standard,the design of 21 kinds of BCH code serial software encoder and decoder and hardware encoder and decoder are realized.Firstly,the encoder based on modulus reduction algorithm and the decoder based on BM iterative algorithm are designed in software.It can realize the coding and decoding of 21 BCH codes in DVB-S2.The correctness of the encoding and decoding algorithm was verified.And it provides a reference for hardware simulation results.Furthermore,the hardware encoder based on the dividing circuit and the decoder including the syndrome calculation circuit,the error position polynomial circuit and the chien-search circuit are further designed.The accuracy of the function was confirmed by comparing the simulation results with the software results.Using ISE Synthesis to analysis of the performance of the hardware circuit.Finally using Xilinx's FPGA to verify the hardware design.First,a test platform for encoders and decoders was built.Then Using ROM to store the information source generated by the random function and using RAM to store the decoding result.Finally,Comparing the data in ROM and RAM to verify the correctness of the encoder and decoder.