Design And Verification Of RapidIO Interface Based On AHB Bus

As a new generation of high speed interconnect bus with the characteristics of high performance,less external pins and strong reliability,RapidIO is widely used in the design of high performance SoC(System on Chip).RapidIO technology alleviates the contradiction between the traditional bus with slow development and the processor with high performance.This project focuses on the interconnection between RapidIO and system on chip in an embedded communication processor chip,and choose AHB(Advanced High Performance Bus)bus as the interlinkage on-chip bus in order to meet the demand of RapidIO for transmission speed.And how to achieve the transformation between AHB operations and RapidIO transactions has become the focus of the research.This paper proposes an interface design scheme to connect AHB bus and RapidIO.Then verifys the correctness and completeness of the design,and ensures that the specification performance of the design is achieved.The mainly works of this paper are as follows:First of all,this paper studies the RapidIO protocol and AHB bus protocol deeply.In this paper,the RapidIO transaction type,packet format,transfer mechanism and logic layer timing are analyzed in detail.At the same time,the protocol contents such as bus interconnection,decoding,operation type,and the timing of control cycle and data cycle in AHB protocol are described in detail.Then,according to the application requirement of the embedded communication processor chip to RapidIO,this paper divides the interface into two modules: the master interface and the slave interface.The master interface actualizes the connection between AHB bus and RapidIO logic layer Initiator port.It converts the AHB bus operations into RapidIO transactions,and the RapidIO operation type can be configured by software.Meanwhile,it supports AHB bus to send doorbell transaction to RapidIO.The connection between Target port of RapidIO logic layer and AHB bus is implemented by the slave interface.It converts the RapidIO transactions into AHB operations.The slave interface can choose the best combination of AHB transfer length and transfer size according to the payload number of the RapidIO transaction,so as to improve the efficiency of interface transmission.It also supports doorbell transaction processing,caches the doorbell information in doorbell transactions,and has the ability to do bus error handling.The paper details theimplementation scheme of the two interface modules.Finally,on the basis of the above research,this paper uses the Verilog to implement the RTL code of the interface,proposes the verification plan according to the design requirements to ensure the functional coverage is up to 100%.Then builds a virtual verification platform,writes the test code,uses NC-Verilog simulation tool to simulate the design of the interface.The simulation result shows that the interface design is correct and the function is complete,which meets the design requirements.