Study On The Characteristics Of NAND Flash Memory

In the era of big data and cloud storage,NAND flash memory requires higher storage densities,faster operation speed and robust reliabilities.However,along with the higher storage density and smaller cell size,some inevitable reliability problems appear due to physical size limitations,such as worse cell-to-cell interference and data retention.On the one side,these limitations make it extremely difficult to increase the storage density anymore when the critical cell size is smaller than 15nm.On the other side,these bring the rapid development of three-dimensional flash memory.In order to understand the intrinsic reliability mechanisms of NAND flash memory,two-dimensional planar NAND flash memory(2D NAND)and three-dimensional stereo memory(3D NAND)are systematically studied in this paper,based on experimental measurements and simulations.The first part of this thesis is to study the reliability of 2D NAND flash memory.Although many scholars have studied the effects of TNL/IPD scaling in NAND flash memories,the effects of ONO IPD scaling on the DR degradation during P/E cycling is still not clear.Therefore.the focus of this part is to study the impacts of ONO IPD thickness on the reliability of 2D HAND flash memory.Firstly,the data retention characteristics of NAND flash memory with various ONO IPD thickness are comparatively studied before and after P/E cycling.It is found that the degradation of threshold voltage(Vth)distributions in memory cells with thinner ONO IPD is much larger than in memory cells with thicker ONO IPD.In simple words,P/E cycling results in larger degradation in memory cells with thinner ONO IPD.Then,with further studies on the capacitors with the same ONO stack layers,it is concluded that P/E cycling could results in higher leakage currents in thinner ONO IPD,which is believed to be the dominate mechanism of Vth distribution degradation.These results indicate that it is necessary to optimize the thickness of IPD layer to improve the memory reliability when scaling 2D NAND flash memory.This work is carried out in Semiconductor Manufactory International Corporation(SMIC),and the results have a good feedback on the process optimization of 2D NAND flash memory.The second part of this thesis is to study the characteristics of 3D NAND flash memory.Although 3D NAND flash memory has been produced in mass,the reliability mechanism of 3D devices needs further exploration and investigations.In order to study the 3D NAND flash memory reliability,vertical gate-all-around(GAA)field-effect-transistors(FETs)with cylinder poly-Si channel are systematically studied.Firstly,transport characteristics of poly-Si channel in vertical GAA poly-Si nanowire FETs are measured.The process of gate stack and poly-Si channel is similar to that of 3D NAND flash memory.The characteristics of temperature dependences and positive bias temperature instability(PBTI)are studied.It is shown that the carrier-transport properties are significantly affected by the defects in the poly-Si nanowire channel.In addition,in the study of PBTI characteristics,it is observed that the interface degradation under a positive stress exists in a short time,while the gate dielectrics degradation persists in a much longer time scale.Secondly,characteristics of 3D NAND flash memory cells are simulated by using the simulation software(Global TCAD Solutions).It is found that the devices deteriorate with the increase of poly-Si channel grain boundary defects.The results indicate that the process optimization of poly-Si channel is important for both vertical GAA poly-Si transistors and 3D NAND flash memories.