The Design And Verification Of Encoder And Decoder Based On DSC

With the rise of mobile internet and the construction of basic network facilities,the demand for high-definition consumer electronics has become higher.High-definition display requires a large amount of data.When the bandwidth is limited,the data transmission capability is low.Therefore,an efficient encoder is required to control the bit rate of the transmitted data.C urrently,there are many video codec standards on the market,but the logic is complex.The hardware that implements these algorithms has a large area in the chip.To solve the problem,the VESA has made the Display Stream Compression(DSC)standard.It not only achieves low-bandwidth transmission with low hardware costs,but also can achieve visually lossless results.This paper makes hardware design and verification according to DSC algorithm.Firstly,the mainstream compression algorithm is introduced,and the characteristics and application of various compression algorithms are analyzed.Secondly,by studying the DSC algorithm,data calculation and principle of each module in the codec are studied.And the basic theory of the application of this paper is determined.Finally,this paper emphasizes the circuit and timing design of each module,at same time,the design module is simulated in turn.This paper explains the practical application of the design.In order to improve the visual effect,the flatness of pixels in the encoder is detected and the quantization parameters are adjusted to ensure the difference between pixels.Then the paper realizes the format conversion function of the codec,supports calculation of RGB and YUV.Three reconfigurable value calculation methods and two coding methods are used to reduce the amount of trans mission data,which greatly reduce the cost of transmission.Meanwhile,the paper adopts the pipeline design and the register struc ture that is similar to the ping-pong buffer.The pipeline satisfies the codec rate requirements and improves the efficiency of data processing.This paper uses a constant rate control method to ensure the same code number of each slice,and improves the stability of the coded data.Besides,it accurately calculates the size of the storage module and reduces the area of hardware design.After the completion of each module design,different test cases are experimented to check that whether the design meets the functional requirements in the verification environment.Through the process of algorithm learning and the design of hardware and verification in this paper,the basic requirements of DSC codec are realized in hardware.The codec supports the calculation of YUV and RGB source forma ts,and achieves encoder 1pixel/clock and decoder 3pixels/clock rate requirements.This peper also supports 2K image resolution with a maximum compression ratio of 3:1.