Research On Tracking Loop Of Beidou Navigation Receiver B1 Signal And Implementation Based-on FPGA

The Beidou satellite navigation system is a global satellite navigation system developed by China.With the continuous improving of this system,its domain has gradually expanded and its application scenarios have been constantly changing.Researching on the algorithm of the Beidou receiver is an important step for accelerating the development of the Beidou navigation system.Capturing and tracking are two important parts in processing baseband signal of BeiDou navigation receivers,and precise tracking of satellite signals is the precondition for resolving navigation information.Targeting D2 navigation message of Beidou II B1 frequency signal,this paper provides a design of the tracking loop for satellite signals.In the first part,the structure of Beidou B1 frequency signal and stimulates the generation of the signal is introduced and analyzed.The next part is the introduction and analysis of effects of high dynamics on the signal tracking loop.Common-used algorithms of identification for three types of discriminators in the loop,PLL discriminator,FLL discriminator,and DLL discriminator,are introduced in this paper.And these algorithms are simulated using Matlab to identify their merits and demerits.The following are covered in the next part of this paper: introduction to carrier tracking loop filter and code tracking loop filter and the operating principles of numerically controlled oscillator;analysis on threshold setting of tracking loops;and introduction to and analysis on choosing methods for bandwidth.On the basis of the above-mentioned analyses,the structure of carrier tracking loop auxiliary code tracking loop is determined to eliminate the impact of dynamic stress on the tracking loop.When designing the carrier tracking loop,FLL is chosen as the auxiliary for PLL because the former has better dynamic tolerance and latter has narrower noise bandwidth.Delay locked loop is used for the implementation of code tracking loop.After the determination of the overall structure,each module of the tracking loop is coded with Verilog language,a hardware description language.When the rationality of each module is confirmed,the tracking loop is stimulated using ISE and modelsim and verified on FPGA for the rationality of the design and its performance.Test results have showed that the designed loop can realize carrier synchronization and pseudo-code synchronization.