Research On Tracking Loop Of Beidou Third Generation Navigation Receiver B2a Signal And Implementation Based-on FPGA

In order to improve China's comprehensive national strength and provide all-weather,high-precision positioning services for global users,China has developed Beidou Satellite Navigation System.The tracking part of baseband signal processing is an indispensable part in navigation system.In this paper,the B2 a band signal of Beidou 3 is studied,and the tracking loop of the satellite signal receiver in this band is analyzed and designed.The main difficulties of satellite navigation receiver are acquisition and tracking.The function of acquisition is to reduce the phase difference between the received signal and the transmitted signal to half of the chip,which is the basis of tracking.The purpose of tracking is to further refine the code phase and carrier frequency,and to achieve real-time tracking and locking of signals.Firstly,the structure of Beidou No.3 B2 a signal is introduced and analyzed.Then,the modules of Beidou navigation system are introduced and their working principles are analyzed.Different loop discriminators are compared,phase-locked loops and frequency-locked loops are studied,their different and applicable scenarios are analyzed,and various algorithms are compared and studied through the simulation of Matlab.By analyzing the characteristics of Beidou No.3 B2 a signal,the structure of carrier tracking loop auxiliary code tracking loop is determined.The structure of carrier tracking loop auxiliary code tracking loop enables the circuit to better adapt to the dynamic environment.In the design of carrier tracking loop,the working characteristics of phase-locked loop and frequency-locked loop are analyzed,and the two loops are combined to determine the second-order frequency-locked loop auxiliary third-order phase-locked loop.The structure of carrier tracking loop and the function of code tracking loop are realized by delayed phase-locked loop.The feasibility of the designed tracking loop is verified by the simulation of Matlab.On this basis,this paper further completes the FPGA implementation and verification of the band tracking loop of BDoo B2 a.Based on the idea of modularity,all the loop structures were first determined,and then each module was designed using the Verilog language.The carrier NCO is used to generate a local carrier having a desired frequency;the lock indication module is configured to detect a frequency and a phase locking result;the loop filter module is configured to perform low pass filtering on the frequency discrimination and phase discrimination results;and the local code generation module is used The signal pseudo-random code of the BeiDou B2 a is generated.After the design is completed,the simulation verifies each module.After the confirmation is correct,the joint loop of ISE and modelsim is performed on the overall loop.Finally,the FPGA board level verification is carried out.The board level test is carried out for the feasibility and performance of the tracking loop design.The test results prove the feasibility of the design.