The Design Of Autocal And Fast-locking PLL With Bandwidth Compensation

Phase-locked loop in recent ten years is widely used in various fields.It can track phase and frequency of input signal,stable frequency of the output clock signal,these abilities make it play an important role in the communication system,the microprocessor and storage circuit,even can directly determine the performance of whole system.With the rapid development in comunication field and microprocessor field in recent ten years,the work frequency of the system has been as high as dozens of Giga Hertz,and chip size shrink continuously,the phase-locked loop circuit is put forward higher requirements.The decreasing of the processor area means that the lower power consumption is needed,the increasing of working frequency means that the better noise performance is needed.charge pump PLL have the characteristics of easy integration,low energy consumption and wide range of capture,so this paper will introduce the theoretical knowledge of charge pump PLL,and design a charge pump PLL which can provide a variable frequency clock for baseband chip.This paper will firstly analyze the basic principle of PLL,loop transmission function,noise and bandwidth,and then discuss the performance of each part of PLL,the different influence on system performance caused by different parameters,the advantages of using switching capacitance as reference source and the realization of VCO with variable tuning curve.Based on the 22 nm Fin FET CMOS process,a low-power PLL which can quickly lock and automatically calibrate the process deviation is designed.After simulate by using Spectre tool,the output clock freqency is from 230.4MHz to 1420.8MHz,the locking time is less than 2μs,phase noise is lower than-80 d Bc/Hz.In this thesis,the switch capacitor circuit is used as the current reference source of the charge pump.Compared with the traditional charge pump PLL which uses the bandgap reference as the reference source,the advantage of this method is the bandwidth of the loop can be compensated by the change of the switch capacitor with the environment,which is beneficial to the stability of the whole system.Compared with the charge pump PLL structure with fixed 1μA current as the reference source,the bandwidth variation of the entire loop is reduced by 44% with the switching capacitor as the reference source structure.In the structure of VCO,the parallel series structure that can be controlled by external digital code is adopted,this structure can expand the output frequency range and keep the control voltage locked in good linear interval.Under all working corners,the VCO control voltage range is within 0.45V~0.65 V.Fin FET have more stringent requirements in reliability,the circuit is simulated to test electrical overstress performance,device aging performance,electro migration,self-heating performance,etc.The simulation results show that the circuit has good working reliability and can meet industrial standards.