Research And Design Of Low Noise Charge Pump Phase-Locked Loop

With the continuous progress of science and technology,people have stepped into the information age.The importance of wireless communication has gradually increased,and more and more attention has been paid to the research of wireless communication technology.With the development of the electronics industry today,how to achieve higher integration,wider scope of application,better stability,and better working performance has become an important criterion for measuring the quality of electronic products.In the wireless transceiver,the phase-locked loop is the circuit module that provides the clock signal inside the chip.Factors such as power consumption,speed and anti-interference capability always affect the performance of the transceiver,and it is an indispensable circuit module in the chip.With the continuous improvement of CMOS technology,more and more RF circuits are integrated on the one chip.The high integration also makes the performance requirements of PLL higher.Therefore,the research on PLL system is of great significance.This article first introduces the development of the phase-locked loop system and its important role in the transceiver,studies the phase noise model of the phase-locked loop system,and the relationship between phase noise and jitter.The phase noise model of the voltage controlled oscillator is analyzed in detail.By comparing and analyzing the structure of different voltage controlled oscillators,a cross-coupled fully differential structure circuit is selected for research.A dynamic threshold voltage technology based on capacitor voltage division is used to improve the phase noise of the circuit,and the frequency modulation range of the circuit is improved through a3-bit switched capacitor array.The other circuit modules are studied and designed in detail,and the main performance indexes of different circuit modules are simulated.At last,a complete phase-locked loop circuit is designed and verified by simulation.The charge pump phase-locked loop proposed in this paper is designed using0.18μm CMOS process technology.It works under the condition of 1.8V power supply voltage and 60 MHz input reference frequency.According to the simulation results,the charge pump phase-locked loop output frequency of this design is 2.4GHz,the power consumption of the circuit is 13.7mW,the reference spur is-70 dB,and the lock time is kept within 15 us.The phase noise of the overall phase-locked loop is only-119.2dBc / Hz at a frequency offset of 1MHz.The phase noise is low.