Design And Implementation Of Image Compression Coding And Decoding Based On FPGA

With the continuous development of computer and information science and technology,image processing plays an important role in aerospace,biomedical science,remote sensing monitoring,information security and other fields,especially the real-time processing of high-resolution image is particularly critical to the development of related fields.Because it takes a lot of time to realize image processing only by using pure software,which can not meet the requirements of speed and real-time,FPGA(field programmable gate array)and Verilog(high efficiency hardware description language)are used The combination of HDL can give full play to the parallel processing ability of pipeline,and then greatly accelerate the design process of the system,providing hardware support and software support.At present,the optimization of image compression algorithm and its hardware implementation still have a lot of research and development space.In this paper,the cyclone II series FPGA is used as the central processor,the DE2 development platform is selected,and the hardware description language is used to program in Quartus II.Finally,an image compression coding and decoding system based on FPGA is designed.The system integrates the functions of image acquisition,JPEG image compression and data transmission.Among them,the D5 M development kit with CMOS sensor MT9P001 chip as the core is selected for image acquisition module to realize image capture and convert Bayer format into RGB format which is easy to operate in real time.The image compression module completes the implementation of JPEG encoder based on FPGA.Therefore,pre-process the image first and convert the RGB format to YCbCr format.Then,based on the Chen algorithm,the addition and subtraction operation symbols are selected through the two-frequency signal controller to reduce the call of the adder,thereby realizing the optimization of the two-dimensional discrete cosine transform(DCT).Secondly,the combination of quantization and Zigzag scanning is used to complete the scanning rearrangement of DCT coefficients and quantization step size,which further saves the time required for function realization.The image transmission module communicates with PC through RS?232 serial port,transmits the compressed image data to PC,decompresses it through MATLAB,displays and saves the image.This paper mainly includes the hardware circuit of image acquisition system,the hardware circuit and software design of JPEG compression processing system.It realizes the function of each module of the system,and tests it to verify the feasibility of the whole system.The final results show that the design achieves the expected function,achieves the design goal,and achieves the requirements of image acquisition,JPEG encoder and transmission.Finally,the image displayed on PC is of good quality,which verifies the correctness of the system.