The Key Technologies Of Low-power Parallel Scan Test And Memory Self-Test

The test quality directly influences the chip yield,cost and customers' satisfaction.The number of transistors' transitions during test mode is multiple times of that in function mode.In another word,it is more possible for chips to have local voltage(IR)drop,thermal hot-spots or even to suffer from irreversible damages.In addition,current commercial tools for memory built-in-self(BIST)test almost place a multiplexer before every input port of the memory.They only focus on the memory's functional timing and ignore its surrounding system lgic,which leads to large area cost and functional timing deterioration.Besides,becausecurrent EDA tools do not provide an efficient test scheme for different kinds of register file,CPU or DSP designers have to implement the test circuit for register file in a full custom way if they want to improve the fault coverage.However,it usually takes a long time and too much effort as well as expense.The YHFT-XX is an innovative DSP of our own country,which integrates varieties of memories,register files as well as function units.So an overall,efficient and chip test scheme is extremely significant for its yield improvement and cost reduction.This paper is aimed to address the three problems mentioned above for YHFT-XX.The major works are listed as below:1、 To reduce the excessive power consumption during scan test,a novel parallel test application architecture is proposed.Compared with the traditional serial scan method,it can save at most 88.98% average power and 59.99% peak power.Meanwhile,introducing the topological information of the circuit into the consideration of the chain connection,this paper proposes an equal-mode compression argorithm.It can increase the parallelism and relieve the demand of scan input/output ports for the parallel architecture further.2、 To save the area cost and minize the timing deterioration induced by test logic,this paper proposes some reusable conditions and corresponding improving methods of the system logic.These methods can not only improve the functional timing closure which contributes to higher speed,but also save the area of the BIST circuit and bypass circuit.Moreover,this paper programs these processes as a software which enables to execute the optimization for BIST circuit automatically,making it more convenient to improve the BIST overhead in other projects.3、 Through analyzing the similarities and differences between memory faults and register file faults,this paper proposes an Extended March C+ argorithm based on the traditional March C+.This new argorithm can cover two major kinds of multiport fault without adding any extra test steps.Besides,by extensive collections of the source RTL code for memory BIST from the commercial EDA tools,this paper successfully designs a BIST circuit for the register file in YHFT-XX with minimum area,including a special comparator.It can support the register file whose number of write and read ports is not equal and read operations are asynchronous.Finally,it develops a simple and convenient BIST generator for register file,which is parameterized and configurable as the commercial EDA tools.As the experiment demonstrates,the BIST circuits generated for the register file can accurately conduct the Extended March C+ algorithm and only account for 3.34% of its total area.So this generator is practical and useful for future industrial chips.