The Design And UVM Verification Of IP Core Base On SpaceWire Protocol

With the success of mass production of semiconductor 7 nm process,the complexity of integrated circuits has reached an unimaginable level,which makes the verification work extremely steeper.Thus,shortening the verification work time and efficiently completing this part of the work have become an urgent need for our industry to solve.The main research objects of this thesis are the SpaceWire protocol and the UVM(Universal Verification Methodology)verification methodology.As a high-speed,full-duplex,full-duplex serial transmission interface,SpaceWire has been used in more and more aerospace electronic systems in recent years.Therefore,it is of great significance to develop an IP core based on the SpaceWire protocol.UVM is currently the most popular verification methodology,providing a range of interfaces and reusability components that are important for improving verification efficiency and achieving complete verification.Based on the SpaceWire standard protocol,the design of the node controller —— CODEC in the IP core has been implemented,and the detailed module-level functional verification on the entire SpaceWire IP core has been completed by using the UVM verification method.For the first part,based on a deep understanding of the SpaceWire protocol,the RTL design of the CODEC is implemented by Verilog HDL.For the first part,learning SystemVerilog and UVM verification methodology,and building a UVM-based SpaceWire reusability verification platform,which mainly includes spw_driver,spw_monitor,spw_codec_model,spw_scoreboard and other reusable components;afterwards,some optimizations have been made.The first is to use virtual interfaces to complete the synchronization of m ultiple excitations,so that the platform can perform registers configuration and normal packet transmission at the same time;the second is to change the analysis_port to FIFO when connecting components;the third is add non-normal incentives in spw_codec_model to achieve the completeness of the entire verification platform.For the final part,the SpaceWire IP core is functionally verified under the verification environment.Writing the sequences for the complete function points that have been extracted,which generate the random excitation with constraints and send them to spw_driver and apb_driver by corresponding sequencer,completing the excitation by apb_if and spw_if;observing the waveform of each test case and the corresponding coverage after simul ation.The test scenario is gradually refined to cover all function points based on changes in coverage.The verification platform has high reusability,clear hierarchy,and good verification completeness.The final VCS simulation results show that the designed IP core meets the SpaceWire protocol requirements,and the module function coverage rate reaches 100%,the code coverage rate is 94.64% as well.After analysis,except for the code that cannot be covered at all,other codes are completely covered.The simulation verification results show that the RTL code achieves the design goals set in the previous period and can be used for the next step.