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Testability Design Of Radiation Hardened SoC

Posted on:2021-04-25Degree:MasterType:Thesis
Country:ChinaCandidate:M H LiFull Text:PDF
GTID:2438330602995009Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of integrated circuit design and aerospace technology,the aerospace-grade system integrated chip technology has been generally valued.At the same time,due to the special test environment of the aerospace-grade system chip in the environment has become increasingly complex,correspondingly,the requirements of chip test are getting higher than before.In recent years,improving the testability and reliability of chips operating in a radiation environment has become a research hotspot.The thesis based on the radiation effects caused by the space radiation environment in which the space equipment operates.The influence degree of radiation effects on semiconductor devices is different,the combination structure of DICE unit and C unit is used at the circuit level,and the protection ring structure is used at the layout level.Moreover,based on the physical design criteria of the SMIC 0.18 μm process,completes the hardening design of scanning D-flip-flops and verifies the radiation resistance of the unit.Refers to the commercial SMIC 0.18 μm process standard cell structure composition,extract the physical information and timing information of the layout,complete the establishment of radiation resistance standard cell library.It is used in the testability design of radiation-resistant reinforced So C chips.A more reasonable test method was selected,due to the particularity of the ARM-Cortex-M3 radiation hardening So C chip.According,the logic function part uses the scan test,and optimizes its test structure,use the compression scan test method.The two methods are compared in terms of test coverage and test time.In this thesis,when designing the MBIST test structure for embedded SRAM in So C,from the two aspects of reducing test time and reducing power,the March C + algorithm that can cover most common failure models is adopted,and the simulation results show the correctness of the March C+ algorithm applied in MBIST design,making SRAM have self-testing function.
Keywords/Search Tags:Radiation Resistant Flip-Flop, System on Chip, Design for Testability, Scan Test Compression, Build-in-self Test
PDF Full Text Request
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