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Design And Implementation Of Image Compression Storage Based On FPGA

Posted on:2020-07-08Degree:MasterType:Thesis
Country:ChinaCandidate:T LiuFull Text:PDF
GTID:2438330626453248Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
The FPGA implementation of the image compression storage system can meet the requirements of miniaturization,low power consumption,and high-speed processing of large amounts of data on the spaceborne system.The JPEG 2000 compression algorithm is also an algorithm for compressing spaceborne systems with its extremely low compression bit rate,excellent single-bit stream compression quality,ability to process very large images without tiling,and strong error correction capability in high-noise channel transmission.The system adopts the structure that the FPGA is the control center,the ADV212 is the core compression device,and the eMMC is the main storage device.In this paper,the complete scheme of the system is designed according to the functional requirements of the subject,including the module division and data processing flow of the system.In image data preprocessing,in order to avoid the serious problem of the neighboring interpolation method,the selection method of its reference pixels is improved.Using MATLAB to simulate and compare various algorithms,it is verified that the improved adjacent interpolation method has good interpolation effect and is suitable for hardware implementation.In the image compression,in order to complete the JPEG 2000 compression of the still image,the basic configuration of the HIPI mode of the ADV212 chip and the flow of the code stream are analyzed,and the details encountered in the debugging are explained in detail.In the FPGA implementation of eMMC storage,for the problem that the eMMC timing instability makes it difficult to speed up,a series of methods for stabilizing the timing and streamlining the configuration process are adopted,so that the transmission speed of the eMMC reaches the index of 100 MB/s.Finally,the system is built and implemented in the Vivado 2018.1 platform.The system physical map,circuit design diagram,timing diagram of the debug tool capture and the image of the final output camera are given.The result verifies that the system can complete the function of image compression storage,and has the function of controlling the image size and controlling the amount of data transmitted to control the image clarity.
Keywords/Search Tags:Image compression, FPGA, ADV212, eMMC
PDF Full Text Request
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