| Manufacturing process variation in deep sub micron (DSM) designs is making it hard to accurately predict the most important design parameters like performance and power. The timing frequency is not deterministic anymore. The constant reduction in transistor sizes has lead to a state where the transistor sizes (length and width), threshold voltages, and various device parameters are not predictable any more. The delays of transistors are now taken as random variables instead of the fixed constant values. As a result, designers are now using probabilistic models for timing delay and using statistical analysis to compute the critical path delay. Techniques like statistical static timing analysis (SSTA) are now widely used to compute the maximum clock frequency. While many techniques are available to handle process variation at circuit level, system level techniques handling process variations are still to develop. We believe the system level techniques for handling process variations are important. This dissertation looks at various problems at system level under process variation to improve timing closure and increase timing yield. The objective of this thesis is to incorporate parametric yield optimizations in various design steps. The main target architecture for this work is the configurable MPSoC platforms in which the processors can be configured to adapt to application needs. Configurable MPSoC are becoming more popular due to their good trade-off between flexibility, efficiency and design turn-around time. A typical MPSoC consists of multiple processors, co-processors, and memory blocks, connected together through communication architecture, like hierarchical buses, direct link FIFOs, or a complete network on chip (NoC). This dissertation uses the adaptability of these systems to handle the effects of within-die variations to improve the overall parametric yield of the system. This work shows that it is important to manage process variations in system level design. If process variation is managed early, it has a high impact on improving yield of the system. If the parametric yield of the system is not considered, then the system can suffer from failures in lot of chips. |
