Digital circuit functional verification using VHDL

In this age, with integrated circuits consisting of millions of gates, verification of the design amounts up to 70% of the effort put into design. As the design complexity is getting higher, the verification technique of the system is the critical step for digital system design and also an increasingly difficult and laborious task. The design activity is more and more supported by hardware description languages, like VHDL; hence, the testing activity needs to pursue this trend.;This thesis focuses on implementation and verification of the benchmark circuit, 16x16 multiplier ISCAS-85 c6288. The Altera Quartus II is used for this implementation. Each component in this circuit is designed using VHDL code, which is a hardware descriptive language. The code is compiled and then simulated. The functional verification of the circuit is done with a VHDL testbench code. ModelSim from Mentor Graphics is the simulation tool used to verify the circuit.