Design Of Verification Platform Of High-speed Data Switching Circuit Based On UVM

Nowadays,as the significant increasing of the complexity and scale of System on Chip(SOC)design,verification work has been a limiting factor for the chip and plays an important role,and building a high efficient platform is the key technique of improving the verification efficiency.This article adopts the Universal Verification Methodology,which is latest proposed by the industry to build a efficient verification platform for optical fiber communication data exchange circuit for the first time and reachs the target of coverage convergence.Besids,this article verifys platform components for abstract reusable public libraries,lays a solid foundation for the following-up work.Combining the verification process of a high-speed serial data network switches SOC chip,this paper introduces UVM verification method based platform to learn the components of the design process and integrated approach.At first,this article introduces the advantages and disadvantages of diversified verification language and verification method,and then this paper describes some verification key technologies and key mechanisms of UVM verification methodology were discussed.In the design process of verification platform,based on the methodology and UVM SystemVerilog language,a reusable UVM platform is designed to support high-speed serial data communication protocol,and eventually combines with SOC processor model and other functional models to achieve hardware and software co-simulation,in order to simulate SOC work,and finally we realize automating simulation work through TCL scripting language and makefile.Considering switch ports is numerous and communications environment is complex,this paper completes the constrained random stimulus target,automatic calibration result and coverage collection.Finally,in the actual project work,based on the extracted function test points we creates different testcases and completes virtual simulation though simulation software,and give full play to prove UVM methodology in the verification work advantage.