The Bus Monitor Circuit Verification Technique Based On UVM

The complexity of chip design continues to increase, and verification occupies more workload than the design part.As the acceleration of research and the continuous shrink of chip development cycles, minimizing the verification time and improving verification productivity have become a serious problem to be solved, which is attached great importance by the industry. Under this background, this paper focuses on the bus monitor circuit verification technique based on UVM.Based on the demand analysis for bus monitor circuit verification and different application scenarios, this paper determines the verification policies and methods of bus monitor circuit, and completes the logical structure of verification platform design. By using the key UVM technologies such as sequence mechanism and phase mechanism, sequencer components, drive components, monitors parts and other verification units are designed with System Verilog verification language. Verification platform that integrated verification units will separate the sequencer and drive of test stimulus and reduce the probability of verification platform errors. It can also achieve incentive injection, printing verification results comparison, automatic operation of the verification environment and precise control of the behavior of the under test design. Based on the distribution of functionality points and extraction results of bus monitor circuit, this paper set four categories of tests including the basic resource test, the bus monitor messages polling function test and the detailed functionality test, with 102 validation cases. Directed numerical test and random test methods are combined to verify bus monitor circuit simulation, and the coverage report is automatically generated. The analysis of the report indicates that the bus monitor circuit verification platform has the correct functionality, and is able to meet the requirements.Bus monitor circuit functional coverage reached 100%, and the code coverage reached 97.03%, which satisfied the required verification specification. Compared with traditional verification platforms, 30% of settings of verification use cases are decreased, and verification time is reduced by about 20%. This platform can be multiplexed to system-level or other sub-system verification platforms, which can effectively reduce the verification time and improve work efficiency.