Validated Monte Carlo based analysis on circuit netlist and zero suppressed binary decision diagrams

Due to the impact of process variations, timing characteristics of chip is uncertain due to uncertainty in delay of many gates. Gate delays are modeled as Probability Density Functions at discrete time points. Therefore Validated Monte Carlo based analysis is conducted on Circuit Netlist to Calculate Probability Density Function at Circuit output with varying Probability Density Function at internal gates. This Monte Carlo analysis is extended to Zero Suppressed Binary Decision Diagrams for the purpose of calculating Probability Density Function accurately at circuit output. In Monte Carlo analysis on Zero Suppressed Binary Decision Diagrams each and every circuit path is stored implicitly. Future work will apply the presented statistical timing analysis process on ZBDDs that contain only sensitized paths. This will be done for purpose of obtaining more accurate (less pessimistic) statistical analysis.