Reconfigurable VLSI architecture and design for digit-serial DSP applications

Field Programmable Gate Arrays (FPGAs) are of great interest for implementing digital signal processing (DSP) systems, due to their attractive features such as reprogrammability and fast time to market. This thesis proposes implementations of digit-serial DSP systems which are compact and efficient on FPGAs. We develop a careful digit-serial circuit implementation strategy which exhibits high performance and which maximizes the device utilization of each FPGA. In addition, a method of implementing digit-serial DSP architectures on FPGAs is presented, and their performance is evaluated with the objective of finding and developing the most efficient digit-serial DSP architectures on FPGAs.; As FPGA technology has steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of Forward Error Correction applications. In particular, Reed-Solomon (RS) encoder/decoder architectures, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migration to FPGA technology. This thesis presents FPGA implementations of an 8-error correcting RS(255, 239) encoder/decoder architectures.; This thesis also presents a novel Digit-Serial FPGA (DS-FPGA) architecture that is optimized for efficient implementations of digit-serial DSP applications. The methodology used for development of this new DS-FPGA architecture is based on an analysis of a large set of digit-serial benchmark circuits, in which we determine the types of logic resources that best match the needs of these circuits. We examine the various circuits used in digit-serial DSP designs to extract their key features that should be reflected in the new FPGA architecture. We explain the design methodology, layout and implementation of the DS-FPGA architecture. We present results for a number of mapping schemes in order to evaluate the benefits of the DS-FPGA. According to our results, the DS-FPGA architecture is more area-efficient and faster than general-purpose FPGAs by a factor of 2.5∼3 for the set of digit-serial benchmark circuits that are considered.