Research And Implementation Of A High Speed Data Recorder

The development of high-speed recorders is changing with each passing day.As an indispensable part of data storage during aircraft flight,recorders play a vital role in analyzing aircraft performance and other parameters.The aircraft may encounter unexpected situations during flight,which is important for recording.Research on the data in the aircraft can provide a theoretical basis for the optimal design of the aircraft,and avoid accidental risks as much as possible.The high-speed data recording device designed in this paper is composed of an acquisition/editor,memory,ground test bench,and supporting upper computer software.The design focuses on the interface circuit between the acquisition/editor and the test bench,highspeed signal transmission,and memory storage methods.The high-speed data recording device needs to collect and store 4 synchronous RS-422 data and 1 LVDS data,and the transmission speed of 422 signals per channel reaches 10Mb/s,using the HDLC interface protocol;CRC verification is used to ensure the data reliability of LVDS signal;Ethernet interface is used to transmit data between host computer and memory,acquisition and editing device and memory.Protocol chip W5300 and TCP/IP transmission protocol are used to ensure that the read back rate can reach more than 90MB/s;The command and working status are transmitted between the test bench and the acquisition and editing device through 1553 B bus to ensure that the transmission results meet the expectations;The memory records the data before and during flight,processes the bad block in flash chip,and checks the error code generated in the storage process with the storage speed of more than 30MB/s.This paper optimizes the FPGA program firmware update design and Flash programming method.FPGA firmware update enables data transmission between the host computer and FPGA through the TCP protocol,which improves the reliability.The design content includes FPGA configuration circuit,firmware update logic design,program storage Flash chip M25P64 read and write process;Flash programming adopts optimized multi-plane pipeline The writeby-erasing method can retain the original data and improve the Flash programming speed.Finally,the function of the high-speed data logger system was tested,and the test verified that the high-speed data logger satisfies the design indicators and reached good expectations;analyzed the reasons for the abnormal program update problems caused by the disconnection of the network and the power during the equipment debugging.,Propose feasible solutions.