Design Of Transient-Enhanced DLDO Circuit

After entering the era of Industry 4.0,electronic devices are required to have the characteristics of miniaturization,high endurance,and multi-function.As one of important parts of electronic devices,power management modules face a series of design challenges including high integration,low power consumption and fast transient response.Low-dropout regulators(LDOs)as the key part of power management modules,continue to innovate in new challenges.Traditional analog LDOs(ALDOs)usually use a negative feedback loop composed of error amplifiers and other units to adjust the voltage.However,at near-threshold operating voltages regions(around0.5V),both error amplifiers and ALDO face huge design challenges.In order to enable the LDO to operate at a voltage of 0.5V,a digital LDO(DLDO)circuit architecture has been proposed.Although the circuit has extremely low static power consumption,the transient response characteristic needs to be further improved without an off-chip capacitor.This thesis firstly introduces the performance parameters of DLDOs.Based on the transient response characteristics of DLDOs,the advantages and disadvantages of related other state-of-theart works are then investigated.To enhance the transient characteristics of DLDOs while meeting the design requirements of low power consumption and high integration,two aspect improvements have been proposed in the thesis.On the one hand,this thesis proposes a bisection method(BM)control scheme to enhance the transient response speed.In steady-state period,only one switch is changed at each clock in the proposed DLDO for keeping high accuracy output voltage.When output voltage transient is detected,the BM control is triggered and find the desire output voltage in a constant step.On the other hand,three kinds of transient response voltage compensation schemes have been presented to improve the transient output voultage in the proposed DLDO and obtain an improvement in a certain extent.The proposed DLDO is fabricated and tested verification using 65 nm CMOS process.The measurement results show that when the input voltage is 0.6V,the output voltage is 0.55 V,and the sampling clock is 10 MHz,with the load current switching between 0.1m A and 4.5m A in 10 ns,the proposed digital LDO shows a transient response time of 5.9μs with a maximum undershoots of118 m V.The current efficiency is 99.7% and the figure of merit(FOM)is 62.2ps.