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Design And Research Of Low Power Consumption,Fast Transient Response LDO

Posted on:2022-01-17Degree:MasterType:Thesis
Country:ChinaCandidate:X LuoFull Text:PDF
GTID:2492306602966979Subject:Master of Engineering
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With the speedy development of integrated circuits urges the technology of electronic products to face constant innovation.In integrated circuits,circuit modules all need a power management system to provide a stable voltage.Among them,LDO,DC/DC converters,AC/DC converters,charge pumps,etc.are all in the power management system Plays an important role in it.LDO is a kind of circuit module.The circuit has the advantages of simple structure,low cost,and superior circuit performance,which makes it occupy an important position in IC power supply design.In the actual LDO circuit,there are many problems that affect the performance of the LDO.By designing some performance-enhancing circuits to solve the problems of high power consumption,large noise,and slow transient response in LDO circuits is of great significance to the development of LDO circuits.Aimed at the problem of high power consumption in the LDO circuit,this article adopts a symmetrical error amplifier structure to reduce the system power consumption while increasing the unit gain bandwidth of the system and improving the transient response speed of the system.The composition and working state of triode and the MOS transistor are compared and analyzed,and the PMOS transistor is selected as the power transistor,which can reduce the static current in the system and achieve the purpose of low power consumption.To solve the problem of slow transient response in the LDO circuit,the dynamic bias compensation technology is adopted.When the output voltage of the LDO system jitters,the dynamic bias circuit can provide a part of the current for the power transistor,reduce the time of output voltage change,and improve the transient response of the system.On the basis of in-depth research on the stability of the LDO circuit,ESR zero compensation,feedforward compensation,and Miller compensation techniques are adopted to eliminate the secondary points of the system and improve the stability of the system.In order to provide a reference voltage with zero temperature coefficient for the system,a bandgap reference circuit is designed with self-biased cascode structure,which can reduce the modulation effect of channel of MOS transistor devices in the reference circuit,reduce the noise in the reference circuit and improve the stability of the system.Based on SMIC 0.13μm CMOS process,LDO circuit simulation was carried out.Simulation results show that they work within the 2V to 5V,circuit output rated voltage of 1.81 V,the circuit at light load,the system static electricity consumption is 18.2μA,open loop gain of77.2d B,the system is 85° phase margin,when the load current in a short period of time from10μA to 30 m A,a change to the undershoot voltage is 294 m V,2.7μs transient response time,overshoot voltage is 213 m V,transient response time of 3.7μs.The overall noise of the circuit is 5.448μF/sqrt(Hz),and the power suppression ratio is-70.68 d B at low frequency,-56 d B at 1k Hz,and-23 d B at 1MHz.The simulation results show that the LDO designed in this paper meets the requirements of low power consumption and fast transient state.
Keywords/Search Tags:Low dropout linear regulator, Self-biased cascode, Dynamic bias, Fast transient response
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