Design Of A Low Voltage Ultra-Low Power SAR ADC For Wearable Medical Devices

Traditional medical equipment has large volume,high power consumption and high cost,so it is not convenient to realize long-term and real-time disease monitoring.Wearable medical devices come into being,but their poor endurance has become a major obstacle to their development.ADC is one of the main energy consumption circuits in wearable medical devices,reducing its power consumption will significantly improve the usage time of wearable medical devices,therefore,the design of low power ADC is of great significance.In this paper,the SAR ADC with higher energy efficiency was selected for low power consumption design.The main work is as follows:The design index is determined according to the research and application requirements.The circuit is designed with a low supply voltage of 0.5 V,so that the transistors in the circuit are in the subthreshold region,and the resulting extremely low current plays a key role in reducing the overall power consumption.According to the low frequency characteristics of the common human physiological electrical signals,the sampling rate of 2 k S/s is specially set,under the premise of ensuring the signal characteristics can be sampled,the sampling rate can be reduced as far as possible to achieve the low power requirements.With reference to the relevant low power SAR ADC design at home and abroad,the accuracy of 10 bit is established.The design of each module is completed,especially the low power design of the main power consumption module.The energy consumption formulas of several typical capacitive array DAC are derived,and the structural characteristics and switching strategies of low power DAC are analyzed,a 5-5 segmenting and bitwise splitting DAC capacitor array with only two kinds of potential is selected,which can achieve low power consumption,compared with the traditional structure,the energy consumption is saved about 98.6%.The selection of comparators and SAR logic circuits focuses on dynamic comparators and dynamic SAR logic circuits without static current.In addition,a bootstrap sampling switch is designed to realize high linear sampling.In order to solve the problem of misjudgment of comparator due to improper timing processing in traditional self-oscillating timing sequence,a high energy efficiency control circuit with control state detection function is proposed.The control state detection signal is applied to the SAR logic circuit as one of the conditions of comparator timing sequence generation to generate the correct comparator timing sequence.The simulation results show that the desired results are achieved.In addition,the control circuit module can control the potential of the lower plate of 4 capacitors,which improves the control efficiency and reduces the energy consumption.The layout is designed based on SMIC 0.18 μm CMOS process,the core area of the layout is 840 μm×140 μm.The post-simulation of the layout with parasitic parameters is carried out.The results show that at the supply voltage of 0.5 V and sampling rate of 2 k S/s,the effective number of bits of the circuit can reach 9.68 bits,the power consumption is 15.45 n W,and the figure of merit is 9.42 f J/conv-step.The design has reached the level of related reports at home and abroad.