The Design Of Low-power SAR ADC For Wearable Medical Equipment

With the development of domestic electronic communications technology,traditional medical equipment has begun to be replaced by wearable medical equipment.The medical equipment recognized by the public all has problems with large volume,high power consumption and cost,and is not suitable for long-term and real-time disease monitoring.The emergence of wearable medical equipment has solved the problem of large volume and high cost of traditional medical equipment,but the problem of power consumption has also become the key to the market for wearable medical equipment.Analog to Digital Converter(ADC)as a key circuit in wearable medical devices,its power consumption also occupies a large proportion of overall power consumption of wearable medical devices.To solve the problem of battery life of wearable medical equipment,the research and design of ADC’s low power consumption are particularly important.The paper completes low-power design requirements by studying and designing Successive Approximation Register(SAR)ADC.SAR ADC has the advantages of high energy utilization rate than other types of ADC,which can better adapt to work scenarios of low voltage and low power consumption.This article determines the design indicator by studying the performance requirements of domestic and foreign papers and reference to wearable medical equipment,and optimizes the main performance module of SAR ADC.The overall design of the circuit adopts a differential structure,which inhibits co-mode interference.Aiming at the problem that the switch tube of the sampling switch of the grille pressure is disturbed by various unreasonable characteristics,it proposes a improved grid pressure self-lifting sampling switch to stabilize the threshold voltage of the switch tube and increase the sampling linearity of the circuit.Aiming at the offset voltage problem of the comparator,a twostage preamplified dynamic comparator structure is proposed,which reduces the offset voltage of the comparator,reduces the power consumption of the comparator,and increases the accuracy of the ADC.Aiming at the problem of high switching energy and many capacitor devices in the traditional switching strategy of DAC capacitor array,the popular monotonic switching strategy is combined with the switching strategy based on common-mode voltage,and a monotonic switching strategy based on common-mode voltage is proposed,and the reference voltage adopts three-level switching,and only the reference voltage of one capacitor is converted at a time,which saves 97.7% of switching power consumption and reduces the number of capacitors by 75% compared with the traditional switching strategy.On the SAR control logic circuit,a dynamic SAR control logic circuit is selected to reduce the static power consumption of the circuit and save the area of the chip.Based on the SMIC 0.18 μm CMOS process,this paper uses the Virtuoso tool to design and draws the landscape.The design achieves a 10-bit low-power SAR ADC with a full circuit area of 450 μm × 250 μm.In the simulation process,the power supply voltage is set to 500 m V,the sampling frequency is 5k S/s,and the simulation results after extracting parasitic parameters from the layout show that the effective bits of the SAR ADC designed in this paper can reach 9.51 bits,the power consumption is 52.3n W,the signal-to-noise distortion ratio is 59 d B,the spurious-free dynamic range can reach 86.7d B,and the figure of merit is 14.35 f J/conv-step.