High Reliability Technique Research Of A53 Based On MPSoC

With the development of commercial spaceflight,American Space X,Canada,Germany and other countries have already launched satellites,like Star-Link,with system level reinforced microprocessors which work in orbit normally for years.Because of the demand of miniaturization,anti-radiation and large computational quantity of the commercial satellite,new requirements are put forward for the high computing performance and high reliability of heterogeneous integrated circuit in electricity,heat,force and radiation resistance.For space application,this project mainly considers the computing performance of heterogeneous processors and the radiation resistance in high reliability.The traditional cell library reinforced processor,which maximum processing speed is no more than 500 MHz,can’t meet the requirement.Meanwhile,commercial satellites have not lowered the requirements for chips’ high reliability.Therefore,the purpose of this project is to provide high reliable,high performance GHz CPU program fast.Regarding the radiation effect,a joint study by Sandia National Laboratory and other companies has shown that the anti-total ionizing dose effect of the 16 nm Fin FET process is no longer the main factor of the radiation effect.The single event latch-up effect can be solved well due to the use of SOI or triple-well technology in the design.Therefore,the most prominent radiation effects of advanced process processors are the large area single event upset caused by high integration density and the single event transient highlighted by high-speed processing.With the shrinking of process nodes,the area affected by the single event upset increases.The traditional triple module redundancy at the transistor level of the cell library can no longer meet the design requirements.For system-level reinforced multi-core processor,due to the power ground isolation between multiple cores,single event upset and transient faults will not spread across cores.Therefore,system level reinforced design is the technique which can solve the system problem caused by large area single event upset and single event transient.Based on the design idea,this project proposes a software and hardware collaboration triple module redundancy reinforcement scheme that uses a high-performance quad-core processor as the reinforcement object and FPGA as the auxiliary reinforcement unit.By analyzing the feasibility of achieving system-level reinforcement,its control flow and data flow are independent,which meets the requirements of triple module redundancy design.In the process of implementation of this scheme,there are four main design requirements: one is the triple module redundancy reinforcement design for the hardware core of the quad-core processor;the second is the design of the real-time cooperative voting circuit in the FPGA;the third is the design of data interaction between quad-core processor and FPGA;the fourth is fault injection of two types of processors and the verification of the system.Through the verification of the system,which uses 16 nm process 1.2 GHz quad-core A53 and FPGA heterogeneous MPSoC chip,it can be proved that the collaborative triple module redundancy architecture of CPU,which works at 1.2GHz,is resistant to single event effects,and its synchronization performance reaches us level.The extra time consuming of the additional software reinforcement is less than one order of the project itself which is acceptable on the system.The reinforcement scheme of this subject can well meet the demand of commercial satellites as well as the avionic for high reliability and high performance of the chip and meet market demand quickly.At the same time,it provides a scheme for the rapid realization of system-level reinforcement of microsystem products.It also discusses the design method of high reliability microelectronics.