Research On Single Event Effect And Radiation Hardening In 65nm CMOS Technology

On April 24,2020,the “Tianwen series”of China’s planetary exploration project has officially launched.On July 31,2020,Beidou global navigation satellite system has officially provided services to the world,and China’s space activities are being accelerated.Many integrated circuit systems are needed for spacecraft flight state control and information processing.There are many cosmic particles in space,and these space particles have different degrees of impact or even damage to the integrated circuits in the spacecraft.Therefore,my country’s space technology has put forward urgent requirements for high-performance radiation hardening integrated circuits.With the advancement of science and technology,the size of semiconductor devices has shrunk proportionally,the number of integrated devices per unit area has increased,the resistance and capacitance on the signal path have continued to decrease,the operating frequency of devices has continued to increase,the gate breakdown voltage has continued to decrease,and the operating voltage following the decrease,the power consumption decreases.The node capacitance becomes smaller,and the critical charge for expressing data information continues to decrease.Space particles strike integrated circuits to cause multi-node charge sharing collection.The single event effect has become the main source of soft errors in integrated circuits used in space.Therefore,it is necessary to study the impact of space particles on integrated circuits,and single event effects are an important research field.In this paper,for 65 nm double-well and triple-well CMOS technology,the single-event transients of PMOS and NMOS transistors in double-well and triplewell CMOS technology are studied respectively.According to the large number of applications of inverters in integrated circuits,it are studied that the singleevent single-transient and single-event multi-transient of inverts designed using of double-well and triple-well CMOS technology;According to the excellent radiation resistance performance of the double-well technology inverter,it is studied that the influence of the well contact density and sensitive node density on the radiation hardening performance of SRAM.This paper has obtained the following four research results.(1)The simulation and experimental results show that in the three well 65 nm CMOS technology,when the particle strikes the sensitive node of the integrated circuit,due to the effect of n-type heavily doped n-well,the recombination ratio of unbalanced carriers is increased,the potential of n-well is not significantly reduced,the parasitic bipolar effect of PMOS transistor in three well CMOS technology is weakened,and the radiation hardening performance of the three well CMOS PMOS transistor is improved.This provides a reference for designing integrated circuits using PMOS transistors in triple well 65 nm CMOS technology.(2)The simulation and experimental results show that in the three well 65 nm CMOS technology,because the PN junction between P-well and n-well is reverse biased,when the particle strikes the sensitive node of the integrated circuit,the reverse biased PN junction prevents the hole from diffusing to the substrate,resulting in the p-well potential rising,and the parasitic bipolar effect of the three well NMOS transistor is turned on,which reduces the radiation hardening performance of the three well technology NMOS transistor.This provides a reference for designing integrated circuits using PMOS transistors in triple well 65 nm CMOS technology.(3)The single event effect of double well and triple well CMOS technologies inverters is experimentally investigated.The experimental results show that in the three well CMOS technology,when the particles vertically strike the integrated circuit,the number of single event transients increases,and the single event four transient pulses appear.When the particles strike the integrated circuit with a certain angle,the number of single event transients also increases,and the single event five transient pulses appear at the same time,which reduces the radiation hardening performance of the three well technology inverter.This provides a reference for designing inverter by double well technology.(4)According to the above three research contents,according to the radiation hardening performance of PMOS,NMOS and inverter in double well and triple well technology,the random access memory array are designed by using double well technology and three well technology.The research results show that the density of sensitive nodes and the well contact density have great influence on the single event effect.It is found that the dense well contact density and the sparse sensitive node have a good effect on reducing the single event effect,At the same time,the interleaving distance plays a very good role in reducing the complexity of detection and error correction technology.Through the above four aspects of research,we have a comprehensive understanding of the design of radiation hardening integrated circuits using 65 nm doublewell CMOS and triple-well CMOS technology.These experiments provide theoretical and practical reference for using different CMOS technologies to improve the radiation hardening integrated circuits.