Design Of Digital LDO With Fast Regulation And Low Quiescent Current

Analog LDO is degraded at the near-threshold level input voltages because there may not be sufficient voltage headroom for the analog error amplifier to control the power transistor.The digital LDO has drawn significant attention recently due to its low-voltage operation capability and process scalability.The speed of regulation and quiescent current are proportional to the sampling frequency.So digital LDO faces the tradeoffs between speed of regulation and quiescent current which limited its applications.To address these issues,a stepwise technique is proposed,it combines two widely adopted options,named binary and multiple-unary weighted at the power stage to achieve faster and stable regulation.Binary weighted power stage achieves faster regulation in a lower sampling frequency and multiple-unary achieves stable regulation.So the stepwise technique can both implement fast regulation and low quiescent current.To eliminate the output ripple and reduce the quiescent current,a dead-zone control is adopted.In order to limit voltage undershoot,an asynchronous logic is used in the digital LDO,it will open all power transistor when undershoot is larger than 20m V.A tracking-bound method is utilized to minimize limit cycle oscillation for light loads.The digital LDO is designed in TSMC 40nm CMOS process.The layout area of the DLDO is 0.122mm~2.The clock frequency is 10MHz,and the on-chip capacitor is 200pF.Under typical simulation conditions,TT corner,27°C,the simulated the settling time is 0.6μs.The maximum quiescent current is 8.5μA under FF corner,85°C.The maximum voltage undershoot is 87.8m V with load step of 50μA to 5m A with a 10ns edge under SS corner,85°C.The simulation results show that the design meets the requirements.