Power Management And Optimization Of RISC-Ⅴ Processor

With the open source of RISC-Ⅴ instruction set,there is a boom in CPU design in the field of chip design.RISC-Ⅴ processors are widely used in embedded systems,the internet of things,portable consumer electronics and artificial intelligence.With the continuous improvement of processor performance,the integration,complexity,and power consumption of the processor are increasing.The rapid rise of power consumption not only increases the cost of chip design and operation,but also affects the endurance time of equipment and the reliability and stability of the circuit.Therefore,low-power design has become a factor that designers have to pay attention to.The key problem faced by processor design is how to reduce power consumption under the premise of satisfying performance.A low-power design and research on a high-performance single-core processor system is carried out in this paper.The analysis and test show that the power consumption of the system is mainly concentrated in the processor core and the L2 cache,and the L2 cache power consumption accounts for more than 60% of the total power consumption.According to this structural feature,the main work and results are as follows:Firstly,a system level power management scheme is proposed.Based on the working mode(NORMAL),four low-power modes of IDLE,DEEP＿IDLE,SLEPP and DEEP＿SLEEP are designed to reduce the power consumption of the system by controlling the clock and power of the module under different working modes.The clock gating and power gating technology are used to control the clock and power respectively.The module-level clock gating unit is added to the RTL code,and the power intent is described through UPF.Aiming at the problem that the system is always running at full speed in the NORMAL mode,Dynamic Frequency and Voltage Scaling technology is introduced to optimize the power management scheme.Three operating points of S1,S2 and S3 are designed for the processor to reduce power consumption,which can be selected independently under the premise of satisfying performance.Secondly,the power management unit(PMU)is analyzed and designed,which is used to switch the working mode and adjust the performance operating point.The working mode switching in this paper realized by software and hardware cooperation,and the performance operating point switched by hardware.The voltage and frequency regulation strategy proposed in this paper has good portability because it monitors the system work and lowpower cycle at the same time.The whole switching process is realized by the hardware circuit without the participation of software,so the real-time performance of switching is greatly improved and the burden of the software system is reduced.Lastly,the module-level and system-level simulation of the PMU are carried out,and the results show that the proposed low-power scheme is correct.The power analysis results show that compared with the NORMAL operating mode,the power consumption in the IDLE operating mode is reduced by 31%,and the power consumption in the DEEP＿IDLE and SLEEP operating mode is reduced by two orders of magnitude.The minimum power consumption is only 0.25 m W when the system is shut down.In the normal operation of the system,compared with the full-speed operation of the S1 operating point,the power consumption at the S2 operating point is reduced by 51%,and the power consumption at the S3 operating point is reduced by 76%.The work and results of this paper show that the strategy can effectively reduce the power consumption of the processor system and can be applied to the low power design process of the processor system.