Design And Verification Of A Baseband Chip Fault Location System

In the current rapid development of system-on-chips,more and more IP cores are integrated into So C and the structure is becoming more and more complex,which makes the multi-core So C face huge debugging pressure.As a complex heterogeneous multi-core processor system,the Intel baseband chip implements JTAG scanning technology and Coresight debugging system inside the chip.However,these debugging methods can no longer meet the needs of a large-scale chip system at a single point of error,which need to grasp the on-site state of the entire system and achieve fully observable chip internal resources.In particular,the visualization of specific memory values and peripheral register values is increasingly important for quickly locating the location of a fault for debugging.In order to solve the above problems,we have studied different internal resources of the chip and designed a method of on-chip debugging for multi-core processors to capture the fault scene.This debugging system enables the entire chip system to enter a special debugging mode and maintain a frozen state through the design of different modules and subsystems.And then,This system obtains the status information on each module of the entire chip through the only active main processor to achieve the purpose of capturing the fault scene.The main work of the paper are as follows:First of all,based on the analysis and comparison of the debugging modes and debugging methods of the four different processors,I chose to control all processors to enter the debugging mode by driving the external debugging interface to avoid affecting the state of the chip.Secondly,by analyzing the characteristics of the communication system formed by the No C and the bus,I use the output signal of the multi-core debugging module to drive the Stall signal of the network interface unit,so that the No C no longer receives new bus requests from other initiators and clears the internal data of the No C.Such a design can keep the No C in an idle state to intercept the internal data path of the chip.And then,I use TOPSPIN IP to generate peripherals that support special suspend mode.It freezes the peripherals by turning off the peripheral kernel clock to ensure that it does not affect the fault scene.Finally,the main processor of the chip obtain the unique access right of the chip to realize the visualization inside the chip.After the error module is locked,we can use the embedded system monitor to analyze the internal signals related to the error module.I finally completed the design of the fault location system based on the baseband chip and used UVM verification methodology to write 23 testcases for directed functional test and random test of the design.The final code coverage and feature coverage collection results reached 100%,it shows that the debugging system meets the design requirements.After tapeout,I performed a post-silicon test on the packaged chip using the typical post-silicon tests environment of the Lauterbach hardware debugger and combined with an oscilloscope to monitor the status of 158 key signals for nearly 30 group samplings.The monitoring results show that the status of the key signals is correct and the function of the fault location system is as expected.The successful implementation of this debugging system provides debuggers with a new choice of debugging schemes and greatly reduces the time for on-chip debugging.