Research And Design Of Digital Back-end Based On Anti-radiation SRAM

With the mature development of semiconductor industry and production technology,the process size of logic unit continues to reduce,the critical voltage of digital logic state maintenance continues to decline,and the digital logic soft errors caused by various radiation factors become more and more obvious.Therefore,a proper layout design and clock signal satisfying timing convergence are the important guarantee to overcome the external radiation interference in the physical implementation of digital back-end.Based on the physical design and implementation of a radiation resistant SRAM digital back-end,this thesis makes an in-depth study from the perspective of layout and clock tree synthesis.Based on the basic layout setting,SRAM is designed reasonably,and the parameters of clock tree synthesis are set reasonably on the premise of timing convergence standard.In order to solve the problem of time sequence deterioration after the radiation element is strengthened,the constraints are more intense in the time sequence constraints,and a certain margin value is added appropriately.Based on the comprehensive condition of clock tree,the static time sequence and time sequence path of digital system are analyzed in detail.Based on innovus software,the layout,standard unit placement,timing optimization,clock tree synthesis,real winding and other related processes are carried out.After the back-end physical process,parasitic parameters extraction,static timing analysis optimization,equivalence check,power analysis and so on are carried out to verify the rationality of the design.In this thesis,aiming at the logic signal error of SRAM under the influence of various radiation effects,the back-end physical design of the chip is completed by using the reinforced radiation resistant unit in the 40 nm process.The clock tree synthesis method based on the combination of inverter and buffer is used to make the duty cycle of the clock signal consistent,reduce the delay of the clock network,reduce the units needed by the clock network,and make the timing of the chip better convergence.At the same time,by adding I / O power supply unit,widening power line,increasing the number of power wiring layers and other measures to solve the problem of voltage drop migration,a robust three-dimensional power network is formed,and finally the whole physical design and related verification of the chip are completed.