Design Of Verification Platform For UHF RFID Digital Baseband Processing Unit Based On UVM

In recent decades,with the increase in chip size and complexity,the possibility of introducing errors in IC design has also greatly increased,followed by more arduous verification work.Since traditional verification techniques can no longer meet the growing verification requirements,various verification methodologies have been born.Among them,UVM(Universal Verification Methodology)is currently the most widely used verification methodology.This article builds a UHF RFID digital baseband processing unit verification platform based on UVM verification methodologies.Based on the research of the ISO / IEC 18000-6C UHF RFID protocol and the function of the digital baseband processing unit,the paper formulates a verification plan,builds a C reference model of the UHF RFID baseband signal processing unit based on the standard protocol,and builds a UVM-based verification platform The functions of the various components are implemented.Among them,the direct programming interface(DPI)of the System Verilog language is used to connect the C reference model to the UVM verification platform to realize the mixed simulation of the C language and the System Verilog language.The construction of the C model and UVM hybrid simulation verification platform is the focus of this article.Compared with the traditional verification method based on directional testing,this method can generate a large number of test cases for verification in a short time,so it can effectively improve the verification.Efficiency and shorten verification time.Finally,in the simulation verification,all test cases including constraint-based random excitation and directional excitation based on coverage-driven are run,and the more important waveforms are analyzed.The final simulation results show that the design function is correct,the function coverage rate reaches 100%,the code coverage rate is higher than 95%,and the verification goal is completed.