The Study Of Coverage Driven Verification Method For Switching Chip

In the designing of modern integrated circuit chip, the scale and complexity of logic design shows a rapid growing trend, the difficulty of design implementation will be substantially improved. In order to ensure the correctness of the logic design capabilities of the chip, the need to invest in human and material resources expands more than ever. After a long period of development, verification techniques in many technology have made considerable progress, but there still exist the problem that the updating level of verification tools and verification methods could not meet the level of the design size increase. Verification techniques lag far behind the development of the design verification technology. Verification time takes too long, thus debugging tends to be more difficult, so the functional verification has become a bottleneck restricting the development of large scale integrated circuit. At the same time, two problems of ensuring the integrity of simulation and shortening the verification cycle in order to enhance verification efficiency remain to be solved. Coverage-driven verification methodology is a new verification methodology, which achieves the validation process dominated by coverage and largely shortens the verification time. In addition, it ensures the verification completeness, Until now, the coverage-driven verification technology in the verification has been put in to a wide range of applications, and promotes the forward development of validation method.In this paper, the coverage-driven verification techniques are deeply analyzed and the various factors of the advanced nature of the coverage-driven is discussed in depth. From the angle of traditional directional testing, the theoretical analysis of the practical application of coverage-driven technique's random verification is made. Forefront UVM methodology produced by Accellera of the industry introduces a set of standard System Verilog library method to verification. The application of library achieves the research and development of the platform structure based on the coverage-driven technique. In the four areas of the realization of coverage-driven platform structure, the modeling and analysis of coverage, stimulus generation programs and result-checking mechanisms, the difference between coverage-driven verification method and traditional verification methods is studied. Then the method of decomposing the functional dots is proposed and a complete functional coverage model is built by the analysis of coverage property. In addition, this paper adopts the transaction level modeling method, the level of abstraction of platform environment, the data from the pin level abstraction to the transaction level, by abstracting the underlying details of hidden to achieve highly-automated verification.In the context of the communication port module of Fibre Channel switch chip, the paper discusses the challenges raised by communication port modules to the validation process and proposes a verification strategy of the communication port modules, meanwhile practically verifies the communication port by UVM verification method. The results showed that the coverage-driven verification technology can realize test time reduction to the original time consuming more than 50% ~ 60%, verification rate greatly increased; Coverage of indicators of code coverage achieves 90%, show that in addition to the existence of a few redundant code, has reached streamline design code, after save copy time and resources; functional coverage reached 100%, which indicates that function points have been proven by realizing a complete coverage of 100%, to ensure the validation of completeness. Through the code coverage and the functional coverage combined validation of the technical indicators, the logic design more streamlined and reduce the existence of redundant code, saving the time and resources of post-simulation. Validation to ensure completeness of verification; and reduce the leak rate of verification in degree, and deep design verification can dig more holes. For the communication port module of the simulation test environment, but also to reuse system level verification environment, and to the project team can be used for reference other protocol switch chip verification.