Research On Analog Front-end Circuit For 25 Gb/s Optical Receiver In 40nm CMOS

With the increasing demands for real-time and intuitive communication in modern warfare,traditional cable interconnection system cannot meet the requirements of military communications.Compared with electrical interconnection,optical interconnection has the advantages of large communication capacity,low loss,low crosstalk,and immunity to electromagnetic interference.Therefore,it gradually becomes the main transmission link of modern military communication systems,especially in the field of shipborne communications and weapon guidance systems.Up to date,the transmission rate of optical communication system has developed to the Tbps level,and research on 100 Gb/s optical interconnect chip has become one of the hot topics.Although the optical receivers have been extensively studied in the past two decades,and great progress has been made,there is still a large gap from the frontier in fully integrated optical receivers.Hence,development of 100 Gb/s optical interconnect chips with independent intellectual property rights has great strategic and practical significance for China's national defense modernization and information construction.This thesis focuses on the research of the analog front-end circuit of high-speed optical receiver in 40nm CMOS technology.The main contents include:1.In order to better shield the photodetector(PD)junction capacitance and solve the problem of low voltage margin under the advanced process node,a novel structure with a source feedback common-gate transimpedance amplifier(TIA)was proposed By optimizing the feedback circuit design,a similar shielding effectiveness is achieved as that of regulated cascade(RGC)amplifier,and the-3dB bandwidth is effectively expanded by 1.4 times.Additionally,the voltage margin,the circuit stability and the output voltage swing are improved.Finally,a low power,high swing,wideband transimpedance amplifier structure design was achieved.2.Based on the proposed common-gate TIA with common-source feedback,a high-speed optical receiver analog front-end circuit was designed in TSMC 40nm CMOS technology,which includes a common-gate TIA with common source feedback,interleaved feedback limiting amplifier,DC offset cancellation unit,and output buffer stage with the fT multiplier.The apparent parasitic effects in 40nm process nodes is weaken by adjusting the layout design,and the inductance structure in the layout is applied to form a ?-type network,thus expanding the circuit bandwidth.The post-layout simulation shown that the front-end circuit has a transimpedance gain of 59.6 dB?,the-3dB bandwidth is 20.8 GHz,the power consumption is 46.6 mW.3.The designed analog front-end circuit chip's were implemented by TSMC 40nm CMOS technology,and tested by RF probe,station.The test results shown that the front-end chip has a-3dB bandwidth of 22 GHz,and a transimpedance gain of 55,55 dB?.All ports achieve good impedance matching,and a bit rate of 25 Gb/s has been successfully achieved.The optical receiver chip designed in this thesis will be integrated with commercial PD in follow-up work,and the ultra-high-speed fully integrated optical receiver will be implemented by integrating four channels on the chip.The results of this thesis provide a reference scheme for the future research on 200 Gb/s optical receiver.