Design Of Low Power SAR ADC For Sparse Signals Quantizations

The successive approximation analog-to-digital converter(SAR ADC)is diffusely applied in the current ADC design.It is not only simple in structure,low power consumption,and small on-chip use area.With the development of analog-to-digital converter technology,SAR ADC can achieve a resolution of more than 12 bits and 10M The above conversion rate.In portable and implantable biomedical systems,the research on low-power SAR ADC design technology has attracted increasing attention.Typical bioelectric signal acquisition and quantification systems include:low-noise high-gain amplifiers,ADC,etc.Among them,the ADC is the important part of the system,and its performance has a great influence on the entire system.Therefore,it is very important to design a SAR ADC with low power consumption,miniaturization and superior performance.This article presents a design of a 10-bit low-power consumption SAR ADC.The ADC consists of a SH circuit,a charge redistribution DAC,and a fully dynamic comparator.,and SAR logic.In the design of DAC,the traditional capacitor switch and the existing new capacitor switch strategy are studied,and a pseudo-single-ended low-power capacitor switch strategy is proposed.This greatly reduces the number of required capacitors and the dynamic power consumption in the process of capacitor switching.And the feasibility of the proposed capacitor switching strategy is verified through MATLAB modeling.When the frequency of the sampled bioelectric signal is low,the system adopts a synchronous clock design,which reduces the design difficulty and simplifies the digital logic circuit.Using a full dynamic comparator,it can still maintain better performance under lower power supply voltage and wide common-mode voltage range.Under the 130nm process,the system circuit design and simulation have been completed.The simulation results show that the effective number of bits is about 9.8bit and the SFDR is about 70dB,which basically meets the system design.