Comparison Of Verilog And Chisel Based Design Of Out-of-order Superscalar RISC-V Processors

For the past several years,the processor market has been dominated by proprietary architectures that implement instruction sets that require licensing and payment to obtain a license to use them.the advent of the RISC-V open source instruction set has dramatically reduced the cost in terms of instruction set licensing.As the size of digital circuit designs increases to millions of gates,the industry needs a more efficient approach to digital system design than traditional Hardware Description Language techniques.This approach can improve developer productivity by reducing the complexity of implementing hardware designs and reducing the time consumed in the design flow.To reduce design complexity,the industry has proposed to increase the level of abstraction of the design space from the hardware level at the register transfer level to the high level,object-oriented software level,and Chisel presents a possible solution to this requirement.In this paper,we design a chaotic superscalar pipeline processor,implemented by Verilog and Chisel respectively,supporting the RV32 I instruction set,using global branch history registers,with Gshare branch prediction,dual instruction decoding,register renaming,chaotic and sequential multi-firing,and reorder buffering.Functional verification using vcs simulation and board-level verification using Xilinx Atrix-7 FPGA.The processor is used as a comparison sample to compare the differences between Verilog and Chisel in implementing a scrambled processor by evaluating the processor performance,hardware resource utilization,and code density.In the study of this paper,the performance of Verilog and Chisel implementations are basically the same under the runtime tests with Dhrystone and Coremark as the benchmarks,and the IPC and branch hit rates are relatively close.In the vivado synthesis,Chisel occupies lower hardware resources,and the number of LUTs and LUTRAM occupies less compared to Verilog.The code density of Chisel is nearly doubled compared to Verilog,and the development time is greatly reduced,and the sent instructions are successfully executed and correct data output is returned in the FPGA board-level verification.It also provides a reference for agile development methods for hardware in the post-Moore's Law era.