Investigation Of Hot Carrier Injection Effect In Advanced Transistors Utlizing Array Testing Technology

With the development of integrated circuit technology,the channel size of field-effect transistor(FET)is shrinking,and the reliability of FET becomes increasingly prominent with the increase of electric field intensity and current density.As one of the main mechanisms that affect reliability and cause device failure,hot carrier injection(HCI)has attracted much attention in device reliability research,and the importance of related reliability testing in the whole chip production process has become increasingly prominent.Reliability testing usually models the degradation of devices based on various physical mechanisms.For the hot carrier injection effect,the traditional method is to establish a mathematical and physical model with I-V characteristics as the influence factor through the accelerated stress test,and then the working conditions in line with the actual situation are substituted into the life of the model calculator to evaluate whether it meets the reliability requirements.Using this kind of reliability testing method,the time to complete the whole test process of a test unit is often more than 10000 seconds.Therefore,this kind of traditional method is suitable for the scene with sufficient test time and less devices,but in the actual production process of VLSI,the time of reliability test should be shortened as far as possible.In this context,array testing technology with higher test efficiency emerges as the times require.This paper focuses on the device reliability research of 55 nm and 40 nm process nodes.According to the design rules of core device and IO device,the single transistor device and array device are designed according to the transistor design process and put into production.Then,the new array test technology is used to test the reliability of hot carrier injection effect of the two structures,and the mathematical and physical model is established and analyzed according to JESD standard.At the same time,the advantages and disadvantages of the array test structure are further discussed,and the subsequent improvement scheme is proposed.