Design And Research Of Wideband Fraction-N Phase-Locked Loop Based On Digital Noise Cancellation Algorithm

With the widely application of various communication technologies,the development of phase-locked loops(PLLs)become more and more rapid.The wideband fractional PLLs have wide output frequency and high resolution,and can provide accurate and high-quality clock signals for the system.However,when the bandwidth is large,the quantization noise of the fraction-N PLLs dominates out-of-band,which increases the jitter of the PLL.So how to eliminate the DSM quantization noise in the fraction-N PLL so that it is not limited in wideband applications has become the research direction of many scholars.Therefore,this paper designs a wide bandwidth,high resolution,and low noise fraction-N PLL based on the digital noise elimination algorithm.In order to improve the efficiency of the PLL,we adopt a top-down design method based on the Cadence AMS design platform.After determining the system structure of the PLL according to the design indicators,we established a phase-domain small-signal model,a phase-noise(PN)analysis model and a behavior-level mixed-signal simulation model which can provide design guidance for subsequent specific circuit design.Then using modular design ideas,the paper first realized the structure and function of each module of the wideband fraction-N PLL,and used EDA tool to carry on the simulation verification to its function and sequence.Finally,after the overall circuit is built,the performance of the overall circuit was evaluated by simulation.In order to realize the wide-band fractional PLL,the quantization noise introduced by DSM must be eliminated.In this paper,a 9bit switch-capacitors array is used to build a digital-time converter circuit(DTC)which can compensate for the instantaneous division ratio error,so as to achieve the purpose of eliminating quantization noise.At the same time,in order to reduce the delay of the DTC circuit affected by the switching of the DTC control signal,a DTC-control-signal reset circuit is adopted in the PLL to make switched capacitors are completely discharged before loading the new control signal.It is concluded from theory and experiment that adding DTC circuit can actually reduce the energy of quantization noise,and only very little noise is introduced when DSM quantization noise is successfully eliminated.The gain calibration circuit which based on the sign-error LMS is adopted in this paper to solve the problems caused by the variation of DTC’s LSB under PVT variation.When the DTC’s LSB is offset under PVT,the product of the DTC’s gain and the DTC’s LSB is a period of VCO output by calibrating the gain.In this way,it can be ensured that when the LSB changes,the function of correctly compensating the phase difference of the input clock signal can be realized by adjusting the gain value,and thus the quantization noise can be better eliminated.This article focuses on solving the quantization noise problem in the fractional PLLs.The DTC circuit is designed for phase compensation.The gain self-calibration circuit is used to solve the problem of inconsistent phase compensation of the DTC circuit when the PVT changes.The paper presents a wide-band frac-N PLL with the 24 MHz reference clock and an output signal frequency of 3GHz～6GHz based in 12 nm CMOS IC technology.In the fraction mode,the performance of the PLL is greatly improved.When the output frequency of the PLL is 6019 MHz,the ripple of the output signal frequency is reduced from 25 MHz to 3MHz,and the rms jitter is 2.6 ps.The wideband fraction PLL consumes 18.9m W and its area is 150μm×217μm.