IR Drop Analysis And Optimization Of GPU Based On 7nm Process

With the rapid development of emerging technologies such as the Internet,5G communications,artificial intelligence,cloud computing,and big data,the highperformance Graphics Processing Unit(GPU)has become a research hotspot.The scale of GPU chips with advanced processes continues to expand,and the system integration and clock frequency are further improved.These performance improvements bring new challenges to back-end physical design.Especially in the 7nm process,due to the reduced power supply voltage,narrowed interconnect lines,and increased number of transistors per unit area,the power consumption problem is very serious.High power consumption will cause a serious IR Drop problem inside the chip,causing the insufficient power supply to the logic unit inside the chip,affecting the performance of the chip,and even causing the chip to fail.Therefore,it is particularly important to analyze and optimize the IR Drop of high-performance GPU chips.Based on a core module in a multi-core GPU chip under the TSMC 7nm process,this thesis uses Cadence’s back-end automatic layout and routing tool Innovus to physically implement it,focusing on exploring the chip’s power planning work,with a final scale of about 300,000 gates,the clock frequency is 850.34 MHz.At the same time,the power consumption analysis tool Voltus was used to establish the Power Grid View(PGV),and the IR Drop analysis of the GPU chip was carried out in stages and a full range,including static and dynamic IR Drop analysis,based on the simulation results of IR Drop,the causes of IR Drop hotspots are analyzed,and corresponding optimization methods are put forward according to the generation mechanism.Finally,based on the limitations of the traditional IR Drop optimization scheme in an application,the thesis proposes an IR Drop optimization scheme applied to the whole process of physical design.The main contents are: 1)After the power planning is completed,the power network reliability is evaluated by the early power network distribution analysis method;2)After all standard cells were placed,the optimization of IR Drop is realized by relocating the standard cells that are flipped at the same time in the IR Drop hotspot area;3)The method of clock skew planning is adopted in the clock tree synthesis stage,by reducing the peak current of the chip to achieve the optimization of IR Drop;4)After the routing is completed,use the remaining routing resources to locally enhance the power network to achieve the optimization of IR Drop.In this thesis,the physical implementation scheme based on IR Drop optimization is used to reduce the number of instances with IR Drop violations in the GPU chip from 5215 to 2730,which is 47.7% lower than that before optimization,and the maximum IR Drop value is reduced from 98.257 m V to 32.181 m V,a decrease of 66.076 m V,a drop of about 67.2%,which effectively improves the IR Drop problem in the chip while ensuring that the chip function and timing are not affected,and finally controls the IR Drop of the GPU chip below the expected 5%.At the same time,compared with the traditional optimization scheme,the maximum value of IR Drop is reduced by 16.688 m V,a drop of 34.1%,and the number of instances with IR Drop violations is reduced by 1145,a drop of 29.5%,which further verifies the effectiveness of the physical implementation scheme based on IR Drop optimization.The IR Drop optimization method and results used in this paper can provide a certain technical reference for IR Drop optimization under advanced technology.