MEMC Testability Design Based On Samsung11nm Process

Due to the advancement of semiconductor manufacturing technology,the complexity of chip design and chip performance have reached unprecedented levels,and the cost of chip testing has become more and more important.Therefore,chip testing has become a nano-scale System-on-Chip(SOC).The primary challenge of design.The main reason for the continuous development of chip testing is the huge demand and complex applications in the consumer electronics field,whether it is from digital circuits,RF circuits,memory,to analog and digital-analog mixed signal testing,and these circuits in nanoscale design The mutual influences are the main research directions at present.How to extend battery life and reduce the power consumption of chip operation and testing is also one of the key points of digital circuit research.Therefore,how to effectively test the chip and low-power design is particularly important.In this subject,a module MEMC(Motion Estimation and Motion Compensation)in the TV chip of Shanghai Jingchen Semiconductor Co.,Ltd.is used as the experimental object to perform testability design based on the chip level to ensure that the fault coverage rate of Stuck-at faults reaches more than 95%.The fault coverage rate of Transition-delay faults reaches more than 90%,and on this basis,several solutions are proposed to improve the fault coverage rate,the impact of power consumption on the chip is analyzed,and several solutions to reduce power consumption are proposed.As a soft IP(Intellectual Property)core,the MEMC module has not built its test framework.Therefore,it is necessary to analyze the circuit structure first,through preliminary synthesis to estimate the number of registers and the input and output ports required for testing,and plan GPIO ports at the chip level to meet this Module test requirements,physical partitioning of modules,selection of appropriate process library based on 11 nm process for synthesis,and replacement of scan registers,serial scan chains,insertion of compression logic and on-chip clock controllers during synthesis to achieve a full scan test structure.Modify the netlist to realize GPIO multiplexing,analyze and solve the problem that may reduce the fault coverage in the design.Use clock gating,Multi-bit registers,X-Filling and other technical means to reduce working power consumption.Reduce test power consumption by generating test vectors with low flip rate,and analyze the possibility of reducing test power consumption by Shift Control technology and scan sequencing technology.The innovations in this subject include the following:1.The physical partition design can effectively improve the overall effect,reduce compilation time,and simplify design constraints and scripts.Analyze the relationship between power consumption and performance,select a suitable process library for comprehensive compilation.2.Insert compression logic and effectively solve the limitation of chip GPIO quantity through GPIO multiplexing design to improve test efficiency.3.Realize the chip-level scanning test structure design and analyze and solve the problems encountered in the design process,and propose a solution to improve the fault coverage rate so that the module's Stuck-at faults fault coverage rate reaches more than 95%,and the Transition-delay faults The fault coverage rate reached more than 90%.4.Using clock gating,Muti-bit registers and other means to reduce working power consumption by 31.2%,using simulated annealing algorithm to solve the scanning sequencing problem,and using MT-filling technology to minimize the average power consumption and peak power consumption during the test.Generating test vectors with lower power consumption reduces the average flip rate of the scan chain by 20~35%.