Design And Implementation Of Encrypted UART IP Core On AES Algorithm

In the information age,information security has become a serious issue that cannot be ignored.As the core technology to ensure information security,information encryption occupies an important position in ensuring data communication security.Currently,the implementation methods of information encryption mainly include software and hardware,but the efficiency of the software implementation cannot satisfy people’s demand for information security.Therefore,the research on the hardware implementation of serial communication encryption is of great practical significance to ensure the information security.In this thesis,based on the analyze of block cipher algorithm and serial communication interface,the AES algorithm with the best performance is selected as the encryption algorithm of this design after the comparison of DES,3DES and AES algorithms.The serial communication interface of this design is determined as UART.An encrypted configurable UART IP core supporting AES-128 and compatible with APB bus has been designed.According to the reliability requirements of serial communication,the research object and the overall design scheme of this thesis are determined.In the design of the AES algorithm,a 32-bit data structure is proposed to reduce the area by sharing the overall structure,modules,computing units and other levels.The control module controls the orderly execution of encryption and decryption of the AES algorithm through the state machine.The use of loop unrolling technology in the Sub Bytes module realizes the trade-off between area and performance.In the S-box module,an optimization method of reduced order is adopted,which achieves an object of changing from complex inversion based on GF(2~8)to a relatively simple inversion based on GF[(2~4)~2].This method can reduce the computational complexity and improve the performance of the algorithm.For complex operations in the Mix Columns module,logical resources are optimized by sharing the same matrix.In the Key Expansion module,the area optimization is realized by sharing the Sub Bytes module.In the design of UART,the direct digital synthesis is adopted to improve the accuracy of clock frequency and the 16-level depth of configurable FIFO is used to improve transfer rate.Finally,the configurable UART supporting Ir DA protocol is realized.In Questasim simulation environment,the C++programming language was used to model the system prototype to improve the accuracy of validation.This design utilizes the Xilinx FPGA board to verifies the function of IP core.The results prove that the IP core consumes2162 LUTs,accounting for only 10.39%of the resources on the board and the throughput of AES algorithm reaches 250Mbps.It is concluded that the IP core achieves the area and performance balance of the AES algorithm in serial communication,which meets the expected design goal.