The Verification And Implementation Of IP Core UART Based On UVM

As the contradiction of rising of SOC design complexity and the promotion of time-to-market becomes more and more obvious, functional verification has become a serious challenge of VLSI design. For conventional IC design functional verification occupy more than half of the entire chip design cycle, for integration of large-scale IP-SOC, the functional verification has reached 80% or oven more of the entire cycle. With SOC design has become a trend in today's IC designs, the number of modules used on-chip IP is increasing, while how to quickly verify these IP modules has become a major bottleneck in the aspect of affecting the development of SOC design.This chapter gives a brife overview of core and the status of the current research on IP applications and future trends. At the same time introduces the current state of development and validation of language mainstream technical problems of functional verification such as low efficiency, poor platform reusability, poor reliability and no completeness guarantee and other issues. To solve the above problems, The verification platform which built on the approch of UVM(Universal Verification Methodology) has the advantages of completeness, reliability, and reuse for the IP verification and also can the urgent needs of the modern SOC verification. This paper uses the sample of SOC chip universal asynchronous receiver controller to study how to use the UVM verification methodology to build verification platform. asynchronous receiver controller as an important part of the input and output of the system. It has been widely used in all kinds of So C design, studies how to make use of the UVM test method build UART verification platform has important practical significance and reference value.The major research for validation of the use of pre-built advanced verification methodology implementation requirements and policy module level of verification platform to ensure rapid implementation and verification platform validation process of efficiency, accuracy, sufficiency, etc. After completing the master of all the UVM verification platform architecture, the verification platform UVC(Universal Verification Component) of the structure and function of were being detailed studied and analyzed and the implementation of each component was mainly focused on, so that a reusable, high efficiency, and completeness of the good verification platform ultimately can be built.Basic test was used to analysis the simulation results, and the completeness and correctness of the verification work can be proved by the final report of fraction coverage. This uart verification environment can be transplanted to the subsystem or system-level verification environment, and uses shorter time to complete the verification task. We hope this UART verification platform can be extended to all similar IP core to achieve reusability, or by building the principles and methods of verification platform to direct the building of other verification platform and reduce the period of the entire SOC verification and improve verification efficiency, reduce the actual work of human and material resources to ensure validity that the chip design.