Design And Implementation Of Digital Part Of A Time To Digital Converter Chip

With the development of science and technology in the late 20 th century,people are more and more interested in the method and technology of accurately measuring the time interval between two events.Due to the rapid development of time-of-flight measurement technology,the technology of measuring the time interval of physical events has been widely used in high-energy physics experiments,laser/radio ranging,smart home and other fields.In the current deep submicron technology,digital integrated circuits are faster,smaller in area and lower in power consumption than analog integrated circuits.In the digital circuits designed in this technology,the circuit for measuring the time interval between signals is often the key part.Therefore,it is of great significance to research and design a time to digital converter with high precision and large dynamic range for time interval measurement.In this thesis,the performance of time to digital converter is studied and analyzed to investigate the implementation principle of time to digital converter of different architectures and its advantages and disadvantages,and a digital part of time to digital converter chip driven by START and STOP pulse is designed,which has a three-stage counting structure of coarse-ring counter and reference clock counter,possesses characteristics of high precision and large dynamic range,and can be used in different fields such as flight time measurement.The main research contents and innovations are as follows:(1)According to the requirements of practical application,the system structure and workflow of the digital part of time to digital converter chip are proposed and designed,and the control registers used to store the working parameters and measurement results of the chip and the special SPI communication protocol used for the microcontroller to read and write control registers are defined.(2)A resolution calibration algorithm based on time to digital converter chip is proposed.The resolution calibration algorithm counts the external precise clock through the three-level counting structure in the chip,so that the microcontroller can calculate the real-time resolution of the chip,which solves the problem that the delay unit in the ring counter circuit will fluctuate in different situations.(3)Two measurement modes suitable for different time intervals are proposed.The microcontroller can change the measurement mode of time to digital converter chip by changing the value of the control register.The first measurement mode is suitable for measuring the start and stop pulses with a time interval of 10 ns ～ 500 ns,and the second measurement mode is suitable for measuring the start and stop pulses with a time interval of more than 500 ns.With the combination of the two measurement modes,the chip can be used to measure different time intervals(4)An improved loop delay line structure circuit is proposed,and the core circuit TDC CORE of the digital part of time to digital converter is designed based on this circuit.Compared with the traditional loop delay line circuit,the dynamic range of this circuit is doubled with the same gate level cell.(5)The decoding circuit with compensation function is designed.After analyzing the compensation signal output by the coarse counter,the decoding circuit compensates the result of the coarse and ring counter,which solves the problem that the coarse counter can not count due to the circuit delay and other reasonsAccording to the definition of system level,this thesis completes the design and simulation of TDC CORE circuit,decoding circuit,TDC control circuit and SPI slave interface circuit,and completes the system construction,function simulation,pre simulation,performance analysis and layout design based on 180 nm CMOS process.The simulation results show that the resolution of the chip is 60 ps,the dynamic range is 8ms,and all functions are correct.