Research And Design Of High Precision TDC

With the development of the process of semiconductor manufacturing technology and the reduction of supply voltage,the design of traditional voltage-domain analog circuits has been more and more difficult.The “Digitalization” of integrated circuits has become a trend.The accuracy of time domain quantization has reached picosecond level by making use of advanced integrated circuit technology.The time-domain quantization can benefit more from the development of the process.Time-to-digital converter(TDC)used in circuits can measure time interval,which can convert input time-domain signals into digital signals.TDC has been widely used in many fields such as laser ranging,quantum physics,molecular imaging and so on.The research of high-precision and large-range time measurement technology has become a hot topic.Aiming at the fields which have high requirements for both resolution and measurement range such as Time-of-Flight(To F)measurement,a TDC circuit that gave consideration to both of them was designed.The TDC can work in two modes: mode 1requires an external high-quality reference clock.This mode has a higher measurement range and can overcome the influence of process,voltage and temperature(PVT);Mode2 does not require an external reference clock and has higher resolution.Each of the modes can be used as an independent TDC.The specific work of this thesis is mainly divided into 2 aspects:In terms of design of the TDC,aiming at the problem that traditional TDC was constrained by the mutual restriction of resolution and measurement range,a TDC based on delay-locked loop(DLL)with two-level interpolation was designed in SMIC55 nm CMOS process.The first stage used a multiplying delay-locked loop(MDLL)interpolation structure to improve the measurement range;The simulation results showed that the TDC could realize the resolution of 7.8ps,the measurement range of130 us when the reference clock was 10 MHz and the frequency multiplication factor was25 times.The measured maximum differential non-linearity(DNL)was 0.4LSB.The measured maximum integral non-linearity(INL)was 0.4LSB.Furthermore,aiming at the problem that mode 1 required an external high-quality reference clock,a two-step TDC based on ring structure was designed.The first stage used a differential ring structure for coarse quantization,which improved the measurement range.The simulation results showed that the TDC could realize the resolution of 5.5ps,the measurement range of 5.8us.The measured maximum differential non-linearity(DNL)was 0.5LSB.The measured maximum integral non-linearity(INL)was 1.3LSB.The second stage of the two TDCs used a delay-locked loop(DLL)to generate the control voltage that voltage-controlled delay cells needed and improved the resolution by scaling the load capacitors of the delay cells.In terms of test of the TDC,this thesis gave a TDC chip testing method and flow based on FPGA and built a TDC test platform by XILINX kintex-7 FPGA in order to complete the accuracy test of a TDC chip with interpolator structure.The TDC chip was taped out under the SMIC 0.18 um CMOS process.In addition,aiming at the particularity of the TDC with two-level interpolation structure,an improved code density test algorithm was designed,which could extract the mismatch information of the delay cell.The MATLAB modeling and simulation of the algorithm was completed.